公开(公告)号：US07970602B2

公开(公告)日：2011-06-28

申请号：US11578781

申请日：2006-02-24

申请人： Tadamasa Toma ,  Yoshinori Matsui ,  Shinya Kadono

发明人： Tadamasa Toma ,  Yoshinori Matsui ,  Shinya Kadono

IPC分类号： G10L19/00

CPC分类号： G10L21/038

摘要： A data reproduction device is provided for achieving seamless reproduction of a stream where a validity of a bandwidth extension function is switched in the stream. The data reproduction device includes an input frequency obtainment unit analyzing header information Hdr and obtaining an input frequency FSin, which is the frequency of basic data, an output frequency determination unit performing predetermined processing based on the input frequency FSin and determining an output frequency FSout, which is the sampling frequency of a decoded frame Fdata, and a decoding unit (2003) which, if the SBR function is valid in a frame to be decoded, decodes sample data at the input frequency FSin and extends the bandwidth of the sampling frequency up to the output frequency FSout, while if the SBR function is not valid in the frame, upsamples the decoding result obtained at the input frequency FSin to the output frequency FSout.

摘要翻译： 提供了一种数据再现装置，用于实现在流中切换带宽扩展功能的有效性的流的无缝再现。 数据再现装置包括输入频率获取单元，分析标题信息Hdr，并获得作为基本数据频率的输入频率FSin;输出频率确定单元，基于输入频率FSin执行预定处理，并确定输出频率FSout; 解码帧Fdata的采样频率和解码单元（2003），如果SBR功能在要解码的帧中有效，则以输入频率FSin解码采样数据，并将采样频率的带宽向上扩展 到输出频率FSout，而如果SBR功能在帧中无效，则将在输入频率FSin获得的解码结果上传到输出频率FSout。

公开(公告)号：US20110141789A1

公开(公告)日：2011-06-16

申请号：US13033424

申请日：2011-02-23

申请人： Yoshinori MATSUI ,  Toshio SUGANO ,  Hiroaki IKEDA

发明人： Yoshinori MATSUI ,  Toshio SUGANO ,  Hiroaki IKEDA

IPC分类号： G11C5/02

CPC分类号： G11C11/408 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C7/1051 ,  G11C7/1063 ,  G11C8/12 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/48 ,  H01L23/5384 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/0401

摘要： In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

摘要翻译： 在包括以预定数据宽度和传送速率发送/接收系统数据信号的多个DRAM芯片的存储器模块中，并且发送/接收具有较大数据宽度和较低传输速率的内部数据信号与 系统数据信号，系统数据信号的传输速率受到限制。 构成存储器模块的DRAM的电流消耗大，阻碍速度增加。 对于该存储器模块，多个DRAM芯片堆叠在IO芯片上。 每个DRAM芯片通过贯通电极连接到IO芯片，并且包括用于通过IO芯片相互转换每个DRAM芯片中的系统数据信号和内部数据信号的结构。 因此，可以缩短DRAM芯片之间的布线，并且可以仅在IO芯片上设置具有大电流消耗的DLL。

公开(公告)号：US20110096585A1

公开(公告)日：2011-04-28

申请号：US12910496

申请日：2010-10-22

申请人： Yoshinori MATSUI

发明人： Yoshinori MATSUI

IPC分类号： G11C5/06 ,  G11C7/10 ,  G11C7/06

CPC分类号： G11C5/063 ,  G11C5/025 ,  G11C11/4097

摘要： To provide a semiconductor device including switch transistor provided between a sub-data line and a main data line. Upon transferring data, the semiconductor device supplies a potential of a VPP level to a gate electrode of the switch transistor when causing the switch transistor to be a conductive state, and supplies a potential of a VPERI level to the gate electrode when causing the switch transistor to be a non-conductive state. According to the present invention, because a potential of the gate electrode is not decreased to a VSS level when causing the switch transistor to be a non-conductive state, it is possible to reduce a current required to charge and discharge a gate capacitance of the switch transistor. Furthermore, because the VPP level is supplied to the gate electrode when causing the switch transistor to be a conduction state, a level of a signal after transfer never drops down by the amount of the threshold voltage.

摘要翻译： 提供包括设置在子数据线和主数据线之间的开关晶体管的半导体器件。 在传送数据时，当使开关晶体管成为导通状态时，半导体器件将VPP电平的电位提供给开关晶体管的栅电极，并且当引起开关晶体管时，向栅电极提供VPERI电平的电位 成为非导电状态。 根据本发明，由于当使开关晶体管为非导通状态时，栅电极的电位不降低到VSS电平，所以可以减少对栅极电容充电和放电所需的电流 开关晶体管。 此外，由于当使开关晶体管成为导通状态时VPP电平被提供给栅电极，所以转移后的信号电平不会下降阈值电压的量。

公开(公告)号：US20110095809A1

公开(公告)日：2011-04-28

申请号：US12909327

申请日：2010-10-21

申请人： Yoshinori Matsui

发明人： Yoshinori Matsui

IPC分类号： H03K17/687

CPC分类号： H03K19/0013 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  H03K19/018571

摘要： To include a switch transistor inserted between a data bus and an input end of a signal receiving circuit and turned off when a potential of the data bus reaches VPERI−NVth, and an assist transistor that drives the input end of the signal receiving circuit to have VPERI. According to the present invention, because the switch transistor and the assist transistor assist a receiving operation performed by the signal receiving circuit, amplitude of a transferred signal can be reduced without reducing a transfer rate. With this configuration, power consumed by charging or discharging of the data bus can be reduced.

摘要翻译： 为了包括插入在数据总线和信号接收电路的输入端之间的开关晶体管，并且当数据总线的电位达到VPERI-NVth时截止，并且驱动信号接收电路的输入端的辅助晶体管具有 VPERI。 根据本发明，由于开关晶体管和辅助晶体管辅助由信号接收电路执行的接收操作，所以可以在不降低传输速率的情况下降低传送信号的幅度。 通过这种配置，可以减少数据总线的充电或放电所消耗的功率。

公开(公告)号：US20110078396A1

公开(公告)日：2011-03-31

申请号：US12687694

申请日：2010-01-14

申请人： Yuri Hiraiwa ,  Yoshiyuki Nishi ,  Kenichi Oyamada ,  Yoshinori Matsui

发明人： Yuri Hiraiwa ,  Yoshiyuki Nishi ,  Kenichi Oyamada ,  Yoshinori Matsui

IPC分类号： G06F12/16 ,  G06F12/00

CPC分类号： G06F11/2058 ,  G06F11/2069 ,  G06F11/2076 ,  G06F11/2079 ,  G06F11/2082

摘要： The present invention causes an asynchronous remote copy to work together with storage clustering technology. A host computer program for controlling the asynchronous remote copy carries out an asynchronous remote copy pair operation by asynchronously working together with a switchover instruction of a storage clustering control program that performs a host write-destination volume switchover in a storage clustering environment.

摘要翻译： 本发明使异步远程副本与存储集群技术一起工作。 用于控制异步远程复制的主计算机程序通过与在存储集群环境中执行主机写目标卷切换的存储集群控制程序的切换指令异步地一起执行异步远程拷贝对操作。

公开(公告)号：US20100290758A1

公开(公告)日：2010-11-18

申请号：US12817344

申请日：2010-06-17

申请人： Tadamasa Toma ,  Shinya Kadono ,  Masayasu Iguchi ,  Tomoyuki Okada ,  Yoshinori Matsui ,  Satoshi Kondo ,  Hiroshi Yahata ,  Wataru Ikeda

发明人： Tadamasa Toma ,  Shinya Kadono ,  Masayasu Iguchi ,  Tomoyuki Okada ,  Yoshinori Matsui ,  Satoshi Kondo ,  Hiroshi Yahata ,  Wataru Ikeda

IPC分类号： H04N9/80 ,  H04N7/26

CPC分类号： H04N9/8042 ,  G11B27/3027 ,  G11B27/329 ,  G11B2220/2541 ,  H04N5/85 ,  H04N9/8063 ,  H04N9/8205 ,  H04N9/8227 ,  H04N19/13 ,  H04N19/179 ,  H04N19/61

摘要： A moving image encoding method of encoding a moving image while switching between variable-length encoding schemes. In this method, a continuous unit to be continuously reproduced is determined (S5201), a stream is generated by encoding the moving image without switching between variable-length encoding schemes in the continuous unit (S5202), and management information is generated that includes a first flag information indicating that a variable-length encoding scheme is fixed in the continuous unit (S5204, and S5205).

公开(公告)号：US07796453B2

公开(公告)日：2010-09-14

申请号：US12145240

申请日：2008-06-24

申请人： Yoshiro Riho ,  Hayato Oishi ,  Yoshinori Haraguchi ,  Yoshinori Matsui

发明人： Yoshiro Riho ,  Hayato Oishi ,  Yoshinori Haraguchi ,  Yoshinori Matsui

IPC分类号： G11C11/00

CPC分类号： G11C7/1048 ,  G11C7/1051 ,  G11C7/1069

摘要： A semiconductor device includes a column decoder that generates a column selecting signal that selects any of a plurality of bit line pairs to which memory cells are connected according to a column address that is input; a bit line selecting switch that connects by the column selecting signal any of a plurality of bit line pairs and a data I/O line pair that outputs data that has been read from a memory cell to the outside; a data amplifier that amplifies a voltage differential of a data I/O line pair and outputs data that has been read to an output buffer; a data I/O line switch that is provided in the data I/O lines; an I/O line precharge circuit that precharges a data I/O line pair that is not on the side of the data amplifier; and an amplifier precharge circuit that precharges a data I/O line pair that is on the side of the data amplifier.

摘要翻译： 半导体器件包括：列解码器，根据输入的列地址，生成列选择信号，该列选择信号选择存储单元连接到的多个位线对; 通过列选择信号连接多个位线对的位线选择开关和将从存储单元读出的数据输出到外部的数据I / O线对; 数据放大器，其放大数据I / O线对的电压差，并将已读取的数据输出到输出缓冲器; 在数据I / O线路中提供的数据I / O线路开关; 对不在数据放大器一侧的数据I / O线对进行预充电的I / O线路预充电电路; 以及对数据放大器侧面的数据I / O线对进行预充电的放大器预充电电路。

公开(公告)号：US20100142290A1

公开(公告)日：2010-06-10

申请号：US12707140

申请日：2010-02-17

申请人： Yoshinori MATSUI

发明人： Yoshinori MATSUI

IPC分类号： G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1057

摘要： An outputting transistor circuit of a push-pull structure has an outputting PMOS transistor and an outputting NMOS transistor connected in series between a first power supply and a grounded power supply. In a standby state, a voltage level of a gate terminal of the outputting PMOS transistor is set to a voltage level of a second power supply higher than a voltage level of the first power supply. In an active state, a voltage level of the gate terminal of the outputting PMOS transistor is changed to a voltage level of the first power supply in response to an active command or a read command, or in response to the state of a semiconductor memory device changing to the active state or a read state, and either the outputting PMOS transistor or the outputting NMOS transistor is turned ON in response to a data read signal from a memory cell.

摘要翻译： 推挽结构的输出晶体管电路具有串联连接在第一电源和接地电源之间的输出PMOS晶体管和输出NMOS晶体管。 在待机状态下，输出PMOS晶体管的栅极端子的电压电平被设定为比第一电源的电压电平高的第二电源的电压电平。 在激活状态下，输出PMOS晶体管的栅极端子的电压电平响应于有效命令或读取命令而变为第一电源的电压电平，或者响应于半导体存储器件的状态 改变到活动状态或读取状态，并且响应于来自存储器单元的数据读取信号，输出PMOS晶体管或输出NMOS晶体管导通。

公开(公告)号：US20100103392A1

公开(公告)日：2010-04-29

申请号：US12588618

申请日：2009-10-21

申请人： Yoshinori Matsui ,  Naka Onoda

发明人： Yoshinori Matsui ,  Naka Onoda

IPC分类号： G03B27/52

CPC分类号： G03B27/52 ,  G03F7/70341 ,  G03F7/70925

摘要： The immersion exposure device cleaning method according to the invention includes: placing a dummy wafer onto a stage of the immersion exposure device; and moving the stage while maintaining an immersion solution between the dummy wafer and a projector lens. The dummy wafer includes a substrate and an adsorption area that is formed on the substrate and has higher adsorption power for particles suspended in the supplied immersion solution than the substrate has for the particles.

摘要翻译： 根据本发明的浸渍曝光装置清洁方法包括：将伪晶片放置在浸没曝光装置的台上; 并且在保持虚拟晶片和投影透镜之间的浸没溶液的同时移动台。 伪晶片包括基板和形成在基板上的吸附区域，并且对于悬浮在所提供的浸渍溶液中的颗粒，对于颗粒而言，具有较高的吸附能力。

公开(公告)号：US07688645B2

公开(公告)日：2010-03-30

申请号：US12114034

申请日：2008-05-02

申请人： Yoshinori Matsui

发明人： Yoshinori Matsui

IPC分类号： G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1057

摘要： An outputting transistor circuit of a push-pull structure has an outputting PMOS transistor and an outputting NMOS transistor connected in series between a first power supply and a grounded power supply. In a standby state, a voltage level of a gate terminal of the outputting PMOS transistor is set to a voltage level of a second power supply higher than a voltage level of the first power supply. In an active state, a voltage level of the gate terminal of the outputting PMOS transistor is changed to a voltage level of the first power supply in response to an active command or a read command, or in response to the state of a semiconductor memory device changing to the active state or a read state, and either the outputting PMOS transistor or the outputting NMOS transistor is turned ON in response to a data read signal from a memory cell.

摘要翻译： 推挽结构的输出晶体管电路具有串联连接在第一电源和接地电源之间的输出PMOS晶体管和输出NMOS晶体管。 在待机状态下，输出PMOS晶体管的栅极端子的电压电平被设定为比第一电源的电压电平高的第二电源的电压电平。 在激活状态下，输出PMOS晶体管的栅极端子的电压电平响应于有效命令或读取命令而变为第一电源的电压电平，或者响应于半导体存储器件的状态 改变到活动状态或读取状态，并且响应于来自存储器单元的数据读取信号，输出PMOS晶体管或输出NMOS晶体管导通。