公开(公告)号：US10025721B2

公开(公告)日：2018-07-17

申请号：US14523705

申请日：2014-10-24

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Vydhyanathan Kalyanasundharam ,  Philip Ng ,  Maggie Chan ,  Vincent Cueva ,  Anthony Asaro ,  Jimshed Mirza ,  Greggory D. Donley ,  Bryan Broussard ,  Benjamin Tsien ,  Yaniv Adiri

IPC: G06F12/10 ,  G06F12/12 ,  G06F12/1009 ,  G06F12/1045 ,  G06F13/38

Abstract: The present invention provides for page table access and dirty bit management in hardware via a new atomic test[0] and OR and Mask. The present invention also provides for a gasket that enables ACE to CCI translations. This gasket further provides request translation between ACE and CCI, deadlock avoidance for victim and probe collision, ARM barrier handling, and power management interactions. The present invention also provides a solution for ARM victim/probe collision handling which deadlocks the unified northbridge. These solutions includes a dedicated writeback virtual channel, probes for IO requests using 4-hop protocol, and a WrBack Reorder Ability in MCT where victims update older requests with data as they pass the requests.

公开(公告)号：US20250004653A1

公开(公告)日：2025-01-02

申请号：US18756976

申请日：2024-06-27

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Mark Fowler ,  Anthony Asaro ,  Vydhyanathan Kalyanasundharam

IPC: G06F3/06

Abstract: A processing system including a parallel processing unit selectively allocating pages of memory for interleaving across configurable subsets of channels based on a mode of allocation. In some embodiments, in a first mode, a page of memory is allocated to and interleaved across a plurality of channels, and in a second mode, a page of memory is allocated to and interleaved across a subset of the plurality of channels.

公开(公告)号：US12153958B2

公开(公告)日：2024-11-26

申请号：US18045128

申请日：2022-10-07

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anirudh R. Acharya ,  Michael J. Mantor ,  Rex Eldon McCrary ,  Anthony Asaro ,  Jeffrey Gongxian Cheng ,  Mark Fowler

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/52 ,  G06F9/54 ,  G06F12/1009 ,  G06F12/14 ,  G06T1/20

Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.

公开(公告)号：US20240329720A1

公开(公告)日：2024-10-03

申请号：US18128744

申请日：2023-03-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Gia Tung Phan ,  Ashish Jain ,  Anthony Asaro ,  Dennis Kin-Wah Au

IPC: G06F1/3234 ,  G09G5/00

CPC classification number: G06F1/3265 ,  G09G5/001 ,  G09G5/363 ,  G09G2300/0842 ,  G09G2330/021 ,  G09G2360/123 ,  G09G2360/18

Abstract: An apparatus and method for efficiently managing power consumption among multiple, replicated functional blocks of an integrated circuit. An integrated circuit includes multiple, replicated memories that use separate power domains. Data of a given type is stored in an interleaved manner among the multiple memories. When control circuitry detects an idle state, commands are sent to the multiple memories specifying storing data of the given type in a contiguous manner in the memories connected to multiple functional blocks. Subsequently, the control circuitry transitions all but one of the memories to the sleep state. The memories rotate amongst themselves with a single memory being in the active state and servicing requests based on which data of the given type is targeted by the requests.

公开(公告)号：US12105623B2

公开(公告)日：2024-10-01

申请号：US16225608

申请日：2018-12-19

Applicant: ATI TECHNOLOGIES ULC

Inventor： Anthony Asaro ,  Philip Ng ,  Jeffrey G. Cheng

IPC: G06F12/02 ,  G06F12/1045 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F12/0292 ,  G06F12/1054 ,  G06T1/20 ,  G06T1/60 ,  G06F2212/1044 ,  G06F2212/657

Abstract: An apparatus includes a graphics processing unit (GPU) and a frame buffer. The frame buffer is coupled to the GPU. Based upon initialization of a virtual function, a plurality of pages are mapped into a virtual frame buffer. The plurality of pages are mapped into the virtual frame buffer by using a graphics input/output memory management unit (GIOMMU) and an associated page table.

公开(公告)号：US20240202015A1

公开(公告)日：2024-06-20

申请号：US18066155

申请日：2022-12-14

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Lu Lu ,  Anthony Asaro ,  Gia Tung Phan ,  Gongxian Cheng ,  Philip Ng ,  Yinan Jiang ,  Felix Kuehling

IPC: G06F9/455 ,  G06F9/54

CPC classification number: G06F9/45545 ,  G06F9/45558 ,  G06F9/545 ,  G06F2009/4557 ,  G06F2009/45579

Abstract: In a computing device, a hardware device (e.g., a parallel accelerated processor or graphics processing unit) is coupled to a bus, such as a peripheral component interconnect express (PCIe) bus. The hardware device supports physical partitioning that allows physical resources of the hardware device to be separated into different partitions. Examples of such physical resources include engine resources (e.g., compute resources, direct memory access resources), memory resources (e.g., random access memory), and so forth. Each physical partition is mapped to a physical function that is exposed to a host on the computing device in a manner that is compliant with the bus protocol, allowing software to access the physical partition in a conventional manner based on the bus protocol.

公开(公告)号：US11836091B2

公开(公告)日：2023-12-05

申请号：US16176431

申请日：2018-10-31

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Anthony Asaro ,  Jeffrey G. Cheng ,  Anirudh R. Acharya

IPC: G06F12/10 ,  G06F9/455 ,  G06F12/1009

CPC classification number: G06F12/1009 ,  G06F9/45558 ,  G06F2009/45583 ,  G06F2212/657

Abstract: A processor supports secure memory access in a virtualized computing environment by employing requestor identifiers at bus devices (such as a graphics processing unit) to identify the virtual machine associated with each memory access request. The virtualized computing environment uses the requestor identifiers to control access to different regions of system memory, ensuring that each VM accesses only those regions of memory that the VM is allowed to access. The virtualized computing environment thereby supports efficient memory access by the bus devices while ensuring that the different regions of memory are protected from unauthorized access.

公开(公告)号：US20230097344A1

公开(公告)日：2023-03-30

申请号：US17487247

申请日：2021-09-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Joseph L. Greathouse ,  Alan D. Smith ,  Francisco L. Duran ,  Felix Kuehling ,  Anthony Asaro

IPC: G06F3/06 ,  G06F12/06

Abstract: Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.

公开(公告)号：US11307993B2

公开(公告)日：2022-04-19

申请号：US16200446

申请日：2018-11-26

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Anthony Asaro ,  Richard E. George

IPC: G06F11/07 ,  G06F11/36 ,  G06F9/30 ,  G06F12/1009

Abstract: For one or more stages of execution of a software application at a first processor, a remap vector of a second processor is reconfigured to represent a dynamic mapping of virtual address groups to physical address groups for that stage. Each bit position of the remap vector is configured to store a value indicating whether a corresponding virtual address group is actively mapped to a corresponding physical address group. Address translation operations issued during a stage of execution of the software application are selectively processed based on the configuration of the remap vector for that stage, with the particular value at the bit position of the remap vector associated with the corresponding virtual address group controlling whether processing of the address translation operation is continued to obtain a virtual-to-physical address translation sought by the address translation operation or processing of the address translation operation is ceased and a fault is issued.

公开(公告)号：US11119944B2

公开(公告)日：2021-09-14

申请号：US16443385

申请日：2019-06-17

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anthony Asaro ,  Kevin Normoyle ,  Mark Hummel

IPC: G06F12/10 ,  G06F12/1036 ,  G06F12/08 ,  G06F12/06 ,  G06F12/02 ,  G06F12/109

Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a plurality of processors. The method includes receiving a memory operation from a processor that receives a memory operation from a processor that references an address in a shared memory, mapping the received memory operation to at least one of a plurality of virtual memory pools to produce a mapping result, and providing the mapping result to the processor.