公开(公告)号：US20230315188A1

公开(公告)日：2023-10-05

申请号：US17710521

申请日：2022-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander J. Branover ,  Thomas J. Gibney ,  Mihir Shaileshbhai Doctor ,  Indrani Paul ,  Benjamin Tsien ,  Stephen V. Kosonocky ,  John P. Petry ,  Christopher T. Weaver

IPC: G06F1/3234

CPC classification number: G06F1/3234

Abstract: Methods and systems are disclosed for transitioning, by a hardware-based controller, a system on a chip (SoC) into different power states. Techniques disclosed include tracking, by the controller, metrics associated with the SoC and transitioning, by the controller, the SoC from a first power state to a second power state based on the tracked metrics. Were the total amount of power that is used by at least a portion of the transition between the first power state to the second power state and a time spent in the second power state is less than the total amount of power that would have been used by remaining in the first power state.

公开(公告)号：US11734151B2

公开(公告)日：2023-08-22

申请号：US17357200

申请日：2021-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Pravesh Gupta

IPC: G06F11/34

CPC classification number: G06F11/349 ,  G06F11/3409

Abstract: An integrated circuit (IC) includes a first circuit including a timer for receiving an adjustable clock signal. Responsive to leaving the non-operational power state to enter a power state in which the adjustable clock has a lower frequency than the reference clock, the first circuit adjusts the frequency of the adjustable clock to a frequency higher than the lower frequency, and then receives an elapsed time associated with the non-operational power state and starts the timer using an adjusted timer value.

公开(公告)号：US11703932B2

公开(公告)日：2023-07-18

申请号：US17357047

申请日：2021-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Amit P. Apte

IPC: G06F1/32 ,  G06F1/3234

CPC classification number: G06F1/3234

Abstract: A data fabric routes requests between the plurality of requestors. A probe filter tracks the state of cached lines of memory at a probe filter coupled to the data fabric. Responsive to the data fabric leaving a non-operational power state while all requestors that are probe filter clients are in a non-operational power state, the power management controller delays a probe filter initialization state in which data regarding cached lines is initialized following the non-operational power state.

公开(公告)号：US20230185623A1

公开(公告)日：2023-06-15

申请号：US18164315

申请日：2023-02-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander J. Branover ,  Benjamin Tsien ,  Elliot H. Mednick

IPC: G06F9/50 ,  G06F11/30

CPC classification number: G06F9/5044 ,  G06F9/5094 ,  G06F11/3062 ,  G06F11/3024 ,  G06F2209/508 ,  G06F2209/501

Abstract: A method, system, and apparatus determines whether a task should be relocated from a first processor to a second processor by comparing performance metrics to associated thresholds or by using other indications. The task is relocated from the first processor to the second processor and executed on the second processor based on the com paring.

公开(公告)号：US20230095622A1

公开(公告)日：2023-03-30

申请号：US17485194

申请日：2021-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander J. Branover ,  Indrani Paul ,  Benjamin Tsien ,  Christopher T. Weaver ,  John P. Petry ,  Mihir Shaileshbhai Doctor ,  Thomas J. Gibney

IPC: G06F1/26 ,  G06F13/40

Abstract: A method and apparatus for isolating and restoring general-purpose input/output (GPIO) pads in a computer system includes identifying GPIO pads associated with the region responsive to an entry into a power-down state of a region of a circuit. The GPIO pads are isolated from one or more external circuits. Upon exit from the power-down state, each associated GPIO pad is restored to a current value.

公开(公告)号：US20230031295A1

公开(公告)日：2023-02-02

申请号：US17390475

申请日：2021-07-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Thomas J. Gibney ,  Alexander J. Branover ,  Mihir Shaileshbhai Doctor ,  Xiaojie He ,  Indrani Paul ,  Benjamin Tsien ,  John P. Petry ,  Pitchaiah Katari

IPC: G06F1/324 ,  G06F1/3237 ,  G06F1/3218 ,  G06F1/08

Abstract: A disclosed technique includes triggering entry into a clock bypass mode, in which a bypass clock generator provides clock signals to functional elements and a primary clock generator does not provide clock signals to functional elements; and triggering exit from the clock bypass mode, in which the bypass clock generator does not provide clock signals to the functional elements and the primary clock generator does provide clock signals to the functional elements.

公开(公告)号：US20220091657A1

公开(公告)日：2022-03-24

申请号：US17031739

申请日：2020-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien

IPC: G06F1/3228 ,  G06F9/48

Abstract: Systems, apparatuses, and methods for efficient power management of a multi-node computing system are disclosed. A computing system includes multiple nodes that receive tasks to process. The nodes include a processor, local memory, a power controller, and multiple link interfaces for transferring messages with other nodes across links. Using a distributed approach for power management, negotiation for powering down components of the computing system occurs without performing a centralized system-wide power down. Each node is able to power down its links, its processor and other components regardless of whether other components of the computing system are still active or powered up. A link interface initiates power down of a link with delay or without delay based on a prediction of whether a link idle condition leads to the link interface remaining idle for at least a target idle threshold period of time.

公开(公告)号：US20210200298A1

公开(公告)日：2021-07-01

申请号：US16730252

申请日：2019-12-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander J. Branover ,  Benjamin Tsien

IPC: G06F1/3234 ,  G06F13/16 ,  G06F9/4401 ,  G06F13/28 ,  G06F1/3296 ,  G06F1/3287

Abstract: Methods, devices and systems for power management in a computer processing device are disclosed. The methods may include selecting, by a data fabric, D23 as target state, selecting D3 state by a memory controller, blocking memory access, reducing data fabric and memory controller clocks, reduce SoC voltage, and turning PHY voltage off. The methods may include signaling to wake up the SoC, starting exit flow by ramping up SoC voltage and ramping data fabric and memory controller clocks, unblocking memory access, propagating activity associated with the wake up event to memory, exiting D3 by PHY, and exiting self-refresh by a memory.

公开(公告)号：US20210173715A1

公开(公告)日：2021-06-10

申请号：US16709404

申请日：2019-12-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander J. Branover ,  Benjamin Tsien ,  Elliot H. Mednick

IPC: G06F9/50 ,  G06F11/30

Abstract: A method, system, and apparatus determines that one or more tasks should be relocated from a first processor to a second processor by comparing performance metrics to associated thresholds or by using other indications. To relocate the one or more tasks from the first processor to the second processor, the first processor is stalled and state information from the first processor is copied to the second processor. The second processor uses the state information and then services incoming tasks instead of the first processor.

公开(公告)号：US20190259448A1

公开(公告)日：2019-08-22

申请号：US15902580

申请日：2018-02-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Chintan S. Patel ,  Vamsi Krishna Alla ,  Alan Dodson Smith

IPC: G11C11/406 ,  G06F13/16

CPC classification number: G06F1/3275 ,  G06F1/3287

Abstract: Systems, apparatuses, and methods for using a scoreboard to track updates to configuration state registers are disclosed. A system includes one or more processing nodes, one or more memory devices, a plurality of configuration state registers, and a communication fabric coupled to the processing unit(s) and memory device(s). The system uses a scoreboard to track updates to the configuration state registers during run-time. Prior to a node going into a power-gated state, the system stores only those configuration state registers that have changed. This reduces the amount of data written to memory on each transition into power-gated state, and increases the amount of time the node can spend in the power-gated state. Also, configuration state registers are grouped together to match the memory access granularity, and each group of configuration state registers has a corresponding scoreboard entry.”