公开(公告)号：US11868777B2

公开(公告)日：2024-01-09

申请号：US17123270

申请日：2020-12-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Kalamatianos ,  Michael T. Clark ,  Marius Evers ,  William L. Walker ,  Paul Moyer ,  Jay Fleischman ,  Jagadish B. Kotra

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52

CPC classification number: G06F9/30181 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30138 ,  G06F9/3834 ,  G06F9/3877 ,  G06F9/52

Abstract: Processor-guided execution of offloaded instructions using fixed function operations is disclosed. Instructions designated for remote execution by a target device are received by a processor. Each instruction includes, as an operand, a target register in the target device. The target register may be an architected virtual register. For each of the plurality of instructions, the processor transmits an offload request in the order that the instructions are received. The offload request includes the instruction designated for remote execution. The target device may be, for example, a processing-in-memory device or an accelerator coupled to a memory.

公开(公告)号：US11842199B2

公开(公告)日：2023-12-12

申请号：US16913146

申请日：2020-06-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Greg Sadowski ,  John Kalamatianos ,  Shomit N. Das

IPC: G06F9/38

CPC classification number: G06F9/3871 ,  G06F9/3836 ,  G06F9/3869

Abstract: An asynchronous pipeline includes a first stage and one or more second stages. A controller provides control signals to the first stage to indicate a modification to an operating speed of the first stage. The modification is determined based on a comparison of a completion status of the first stage to one or more completion statuses of the one or more second stages. In some cases, the controller provides control signals indicating modifications to an operating voltage applied to the first stage and a drive strength of a buffer in the first stage. Modules can be used to determine the completion statuses of the first stage and the one or more second stages based on the monitored output signals generated by the stages, output signals from replica critical paths associated with the stages, or a lookup table that indicates estimated completion times.

公开(公告)号：US20230315536A1

公开(公告)日：2023-10-05

申请号：US17708021

申请日：2022-03-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mark Wyse ,  Bradford Michael Beckmann ,  John Kalamatianos ,  Anthony Thomas Gutierrez

IPC: G06F9/50

CPC classification number: G06F9/5077

Abstract: To reduce inter- and intra-instruction register bank access conflicts in parallel processors, a processing system includes a remapping circuit to dynamically remap virtual registers to physical registers of a parallel processor during execution of a wavefront. The remapping circuit remaps virtual registers to physical registers at a register mapping table that holds the current set of virtual to physical register mappings based on a list of available registers indicating which physical registers are available for a new mapping and a register mapping policy.

公开(公告)号：US11726783B2

公开(公告)日：2023-08-15

申请号：US16856832

申请日：2020-04-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Marko Scrbak ,  Mahzabeen Islam ,  John Kalamatianos ,  Jagadish B. Kotra

IPC: G06F9/38 ,  G06F9/26 ,  G06F16/901 ,  G06F12/0893

CPC classification number: G06F9/264 ,  G06F9/262 ,  G06F9/3808 ,  G06F9/3887 ,  G06F12/0893 ,  G06F16/9017

Abstract: A processor includes a micro-operation cache having a plurality of micro-operation cache entries for storing micro-operations decoded from instruction groups and a micro-operation filter having a plurality of micro-operation filter table entries for storing identifiers of instruction groups for which the micro-operations are predicted dead on fill if stored in the micro-operation cache. The micro-operation filter receives an identifier for an instruction group. The micro-operation filter then prevents a copy of the micro-operations from the first instruction group from being stored in the micro-operation cache when a micro-operation filter table entry includes an identifier that matches the first identifier.

公开(公告)号：US20230205872A1

公开(公告)日：2023-06-29

申请号：US17561170

申请日：2021-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadish B. Kotra ,  Onur Kayiran ,  John Kalamatianos ,  Alok Garg

IPC: G06F21/55

CPC classification number: G06F21/554 ,  G06F2221/034

Abstract: A method includes receiving an indication that a number of activations of a memory structure exceeds a threshold number of activations for a time period, and in response to the indication, throttling instruction execution for a thread issuing the activations.

公开(公告)号：US20230024089A1

公开(公告)日：2023-01-26

申请号：US17384646

申请日：2021-07-23

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Ganesh Dasika

IPC: G06F9/30

Abstract: A processing device includes a zero detection circuit to determine that an operand of a first instruction is zero and instruction conversion logic coupled with the zero detection circuit to, in response to the zero detection circuit determining that the operand is zero, convert the first instruction to a register move instruction executable by the processing device.

公开(公告)号：US11550588B2

公开(公告)日：2023-01-10

申请号：US16109195

申请日：2018-08-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Kalamatianos ,  Adithya Yalavarti ,  Varun Agrawal ,  Subhankar Pal ,  Vinesh Srinivasan

IPC: G06F9/38 ,  G06F11/34 ,  G06F1/32 ,  G06F1/3287

Abstract: A branch predictor of a processor includes one or more prediction structures, including a predicted branch address and predicted branch direction, that identify predicted branches. To reduce power consumption, the branch predictor selects one or more of the prediction structures that are not expected to provide useful branch prediction information and filters the selected structures such that the filtered structures are not used for branch prediction. The branch predictor thereby reduces the amount of power used for branch prediction without substantially reducing the accuracy of the predicted branches.

公开(公告)号：US20220100501A1

公开(公告)日：2022-03-31

申请号：US17033883

申请日：2020-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael W. Boyer ,  John Kalamatianos ,  Pritam Majumder

IPC: G06F9/22

Abstract: An electronic device includes a processor having a micro-operation queue, multiple scheduler entries, and scheduler compression logic. When a pair of micro-operations in the micro-operation queue is compressible in accordance with one or more compressibility rules, the scheduler compression logic acquires the pair of micro-operations from the micro-operation queue and stores information from both micro-operations of the pair of micro-operations into different portions in a single scheduler entry. In this way, the scheduler compression logic compresses the pair of micro-operations into the single scheduler entry.

公开(公告)号：US20210334098A1

公开(公告)日：2021-10-28

申请号：US16856832

申请日：2020-04-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Marko Scrbak ,  Mahzabeen Islam ,  John Kalamatianos ,  Jagadish B. Kotra

IPC: G06F9/26 ,  G06F9/38 ,  G06F12/0893 ,  G06F16/901

Abstract: A processor includes a micro-operation cache having a plurality of micro-operation cache entries for storing micro-operations decoded from instruction groups and a micro-operation filter having a plurality of micro-operation filter table entries for storing identifiers of instruction groups for which the micro-operations are predicted dead on fill if stored in the micro-operation cache. The micro-operation filter receives an identifier for an instruction group. The micro-operation filter then prevents a copy of the micro-operations from the first instruction group from being stored in the micro-operation cache when a micro-operation filter table entry includes an identifier that matches the first identifier.

公开(公告)号：US20210279054A1

公开(公告)日：2021-09-09

申请号：US17325067

申请日：2021-05-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadish B. Kotra ,  John Kalamatianos

IPC: G06F9/22 ,  G06F12/0875 ,  G06F9/30

Abstract: Systems, apparatuses, and methods for compacting multiple groups of micro-operations into individual cache lines of a micro-operation cache are disclosed. A processor includes at least a decode unit and a micro-operation cache. When a new group of micro-operations is decoded and ready to be written to the micro-operation cache, the micro-operation cache determines which set is targeted by the new group of micro-operations. If there is a way in this set that can store the new group without evicting any existing group already stored in the way, then the new group is stored into the way with the existing group(s) of micro-operations. Metadata is then updated to indicate that the new group of micro-operations has been written to the way. Additionally, the micro-operation cache manages eviction and replacement policy at the granularity of micro-operation groups rather than at the granularity of cache lines.