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    METHOD AND APPARATUS FOR STORAGE DEVICE WITH A LOGIC UNIT AND METHOD FOR MANUFACTURING SAME
    62.
    发明申请
    METHOD AND APPARATUS FOR STORAGE DEVICE WITH A LOGIC UNIT AND METHOD FOR MANUFACTURING SAME 有权
    具有逻辑单元的存储装置的方法和装置及其制造方法

    公开(公告)号：US20090175100A1

    公开(公告)日：2009-07-09

    申请号：US11971819

    申请日：2008-01-09

    申请人： Christoph Bilger ,  Peter Gregorius ,  Michael Bruennert ,  Maurizio Skerlj ,  Wolfgang Walthes ,  Johannes Stecker ,  Hermann Ruckerbauer ,  Dirk Scheideler ,  Roland Barth

    发明人： Christoph Bilger ,  Peter Gregorius ,  Michael Bruennert ,  Maurizio Skerlj ,  Wolfgang Walthes ,  Johannes Stecker ,  Hermann Ruckerbauer ,  Dirk Scheideler ,  Roland Barth

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1006

    摘要： Method and apparatus that relate to a storage device comprising a plurality of memory cells, an interface device configured to connect the storage device to a host system and configured to transmit signals to read and write data from the host system to the memory cells via a first and second data path, and a logic unit. The logic unit is configured to read and write data from the plurality of memory cells via the second data path, and configured to perform logic operations on data stored in the plurality of memory cells. When performing read and write operations, the first data path excludes the logic unit, and the second data path includes the logic unit. Furthermore, the logic unit is communicatively coupled between the interface device and the plurality of memory cells. Additionally, a method for manufacturing the memory device is provided.

    摘要翻译： 涉及包括多个存储器单元的存储设备的方法和设备，接口设备，被配置为将存储设备连接到主机系统，并且被配置为经由第一个存储器单元将数据从主机系统读取和写入到存储器单元 和第二数据路径，以及逻辑单元。 逻辑单元被配置为经由第二数据路径从多个存储器单元读取和写入数据，并且被配置为对存储在多个存储器单元中的数据执行逻辑运算。 当执行读和写操作时，第一数据路径排除逻辑单元，第二数据路径包括逻辑单元。 此外，逻辑单元通信地耦合在接口设备和多个存储器单元之间。 另外，提供了一种用于制造存储器件的方法。

    Memory Module
    64.
    发明申请
    Memory Module 审中-公开
    内存模块

    公开(公告)号：US20080301370A1

    公开(公告)日：2008-12-04

    申请号：US11757770

    申请日：2007-06-04

    申请人： Srdjan Djordjevic ,  Hermann Ruckerbauer ,  Maurizio Skerlj ,  Christian Mueller

    发明人： Srdjan Djordjevic ,  Hermann Ruckerbauer ,  Maurizio Skerlj ,  Christian Mueller

    IPC分类号： G06F12/00 ,  G06F13/00 ,  H03F21/00

    CPC分类号： G11C5/04 ,  G06F13/1668

    摘要： A memory module includes a module circuit board, an amplifier circuit disposed on the module circuit board for amplifying an input signal, and a memory component to store a data item, wherein the memory component is disposed on the module circuit board. The amplifier circuit includes an input to receive a data signal and an output to provide an amplified data signal. The memory component comprises an input to receive the amplified data signal, wherein the data item is stored in the memory component in dependence on a level of the received amplified data signal.

    摘要翻译： 存储模块包括模块电路板，设置在模块电路板上用于放大输入信号的放大器电路，以及用于存储数据项的存储器组件，其中存储器组件设置在模块电路板上。 放大器电路包括用于接收数据信号的输入端和用于提供放大数据信号的输出端。 存储器组件包括用于接收放大数据信号的输入，其中根据所接收的放大数据信号的电平将数据项存储在存储器组件中。

    Memory module with a clock signal regeneration circuit and a register circuit for temporarily storing the incoming command and address signals
    65.
    发明授权
    Memory module with a clock signal regeneration circuit and a register circuit for temporarily storing the incoming command and address signals 有权
    具有时钟信号再生电路的存储器模块和用于临时存储输入命令和地址信号的寄存器电路

    公开(公告)号：US07334150B2

    公开(公告)日：2008-02-19

    申请号：US11002148

    申请日：2004-12-03

    申请人： Hermann Ruckerbauer ,  Abdallah Bacha ,  Christian Sichert ,  Dominique Savignac ,  Peter Gregorius ,  Paul Wallner

    发明人： Hermann Ruckerbauer ,  Abdallah Bacha ,  Christian Sichert ,  Dominique Savignac ,  Peter Gregorius ,  Paul Wallner

    IPC分类号： G06F1/04

    CPC分类号： G11C5/04 ,  G11C5/063

    摘要： A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command and address signals to the semiconductor memory chips. A clock signal regeneration circuit and a register circuit are arranged on the semiconductor memory module in a common chip packing connected to the bus signal lines. The clock signal regeneration circuit and the register circuit respectively condition the incoming clock signal and temporarily store the incoming command and address signals, respectively multiply the conditioned clock signal and the temporarily stored command and address signals by a factor of 1:X, and respectively supply to the semiconductor memory chips the conditioned clock signal and the temporarily stored command and address signals.

    摘要翻译： 半导体存储器模块包括多个半导体存储器芯片和总线信号线，其向半导体存储器芯片提供输入时钟信号和输入命令和地址信号。 时钟信号再生电路和寄存器电路以连接到总线信号线的公共芯片封装布置在半导体存储器模块中。 时钟信号再生电路和寄存器电路分别对输入的时钟信号进行调节，并临时存储输入的命令和地址信号，分别将经调节的时钟信号和临时存储的命令和地址信号乘以1：X，分别提供 对半导体存储器芯片调节时钟信号和临时存储的命令和地址信号。

    Memory System and Method for Transferring Data Therein
    66.
    发明申请
    Memory System and Method for Transferring Data Therein 有权
    用于传输数据的内存系统和方法

    公开(公告)号：US20080022037A1

    公开(公告)日：2008-01-24

    申请号：US11862915

    申请日：2007-09-27

    申请人： Hermann Ruckerbauer

    发明人： Hermann Ruckerbauer

    IPC分类号： G06F12/02

    CPC分类号： G11C7/1018 ,  G06F13/1684

    摘要： A memory system is functionally designed so that, despite operation without an error correction device, memory chips of a memory module that are actually provided for error correction are concomitantly used for the data transfer. A control device is configured to receive, store and transfer data packets to and from a first and second set of memory chips. Transfer of an internal packet data from the control device to memory takes place such that a first record is stored in a second set of memory chips and additional records are stored in the first set of memory chips. In preferred embodiments, data is allocated in the second set of memory chips such that at least one additional transfer step takes place to the second set of memory chips compared with transfers to the first set of memory chips. In the additional transfer step(s), the first set of memory chips is masked from receiving data.

    摘要翻译： 存储器系统在功能上被设计成使得尽管在没有纠错装置的情况下进行操作，但实际提供用于纠错的存储器模块的存储器芯片被同时用于数据传输。 控制装置被配置为接收，存储和传送数据分组到第一和第二组存储器芯片。 将内部分组数据从控制设备传送到存储器进行，使得第一记录被存储在第二组存储器芯片中，并且附加记录被存储在第一组存储器芯片中。 在优选实施例中，在第二组存储器芯片中分配数据，使得与传送到第一组存储器芯片相比，至少一个额外的转移步骤发生到第二组存储器芯片。 在附加传送步骤中，第一组存储器芯片被从接收数据中被掩蔽。

    Semiconductor memory system and memory module
    68.
    发明申请
    Semiconductor memory system and memory module 审中-公开
    半导体存储器系统和存储器模块

    公开(公告)号：US20070079057A1

    公开(公告)日：2007-04-05

    申请号：US11239829

    申请日：2005-09-30

    申请人： Hermann Ruckerbauer ,  Peter Gregorius

    发明人： Hermann Ruckerbauer ,  Peter Gregorius

    IPC分类号： G06F12/00 ,  G06F13/00

    CPC分类号： G06F13/1673 ,  G06F13/1684

    摘要： A semiconductor memory system is disclosed. In one embodiment, the semiconductor memory system and memory module of the present invention provides a buffer, wherein at least one write buffer chip on the memory module is only buffering and registering write data, command and address signals written from a memory controller to the memory chips. As read data are written back from each memory chip directly to the memory controller through unidirectional point-to-point read data lines the present semiconductor memory system achieves a low latency as compared with a fully buffered DIMM concept. As read data are only unidirectional a high transmission bandwidth can be achieved.

    摘要翻译： 公开了半导体存储器系统。 在一个实施例中，本发明的半导体存储器系统和存储器模块提供了缓冲器，其中存储器模块上的至少一个写入缓冲器芯片仅缓冲并将从存储器控制器写入的写数据，命令和地址信号注册到存储器 筹码 由于读取数据通过单向点对点读取数据线直接从每个存储器芯片写回存储器控制器，与全缓冲DIMM概念相比，本半导体存储器系统实现了低延迟。 由于读取数据只是单向的，所以可以实现高传输带宽。

    Semiconductor memory arrangement with branched control and address bus
    69.
    发明申请
    Semiconductor memory arrangement with branched control and address bus 失效
    具有分支控制和地址总线的半导体存储器

    公开(公告)号：US20070058409A1

    公开(公告)日：2007-03-15

    申请号：US11226448

    申请日：2005-09-15

    申请人： Hermann Ruckerbauer ,  Christian Weiss ,  Ralf Schledz ,  Johannes Stecker

    发明人： Hermann Ruckerbauer ,  Christian Weiss ,  Ralf Schledz ,  Johannes Stecker

    IPC分类号： G11C5/06

    CPC分类号： G11C5/063

    摘要： A semiconductor memory arrangement for operation in a data memory system with at least one semiconductor memory chip for the storage of user data includes a memory controller for control of the at least one semiconductor memory chip, and at least one unidirectional signal line bus for control and address signals connected with the memory controller and branching at least once. The at least once branching bus directly connecting at least one semiconductor memory chip with the memory controller and connecting the semiconductor memory chips among each other.

    摘要翻译： 一种用于在具有用于存储用户数据的至少一个半导体存储器芯片的数据存储器系统中操作的半导体存储器装置包括用于控制至少一个半导体存储器芯片的存储器控​​制器和用于控制的至少一个单向信号线总线， 与存储器控制器连接的地址信号并至少分支一次。 所述至少一次分支总线将至少一个半导体存储器芯片与存储器控制器直接连接并将半导体存储器芯片彼此连接。

    Semiconductor memory module unit for point-to-point data interchange
    70.
    发明申请
    Semiconductor memory module unit for point-to-point data interchange 审中-公开
    用于点对点数据交换的半导体存储器模块单元

    公开(公告)号：US20070033351A1

    公开(公告)日：2007-02-08

    申请号：US11377473

    申请日：2006-03-16

    申请人： Hermann Ruckerbauer

    发明人： Hermann Ruckerbauer

    IPC分类号： G06F13/00

    CPC分类号： G11C5/04

    摘要： The invention describes a semiconductor memory module unit for P2P data interchange with a memory controller. Memory chips having different data widths can be arranged on the semiconductor memory module unit in such a way as to enable a tree-like branching by signal data transmission from a node-like memory chip to a plurality of downstream memory chips while retaining the data width.

    摘要翻译： 本发明描述了一种用于与存储器控制器进行P2P数据交换的半导体存储器模块单元。 具有不同数据宽度的存储芯片可以以这样的方式被布置在半导体存储器模块单元上，使得能够通过从节点状存储器芯片到多个下游存储器芯片的信号数据传输而实现树状分支，同时保持数据宽度 。