利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

135 条记录 (耗时 0.026 秒)

    Memory Module
    1.
    发明申请
    Memory Module 审中-公开
    内存模块

    公开(公告)号：US20080301370A1

    公开(公告)日：2008-12-04

    申请号：US11757770

    申请日：2007-06-04

    申请人： Srdjan Djordjevic ,  Hermann Ruckerbauer ,  Maurizio Skerlj ,  Christian Mueller

    发明人： Srdjan Djordjevic ,  Hermann Ruckerbauer ,  Maurizio Skerlj ,  Christian Mueller

    IPC分类号： G06F12/00 ,  G06F13/00 ,  H03F21/00

    CPC分类号： G11C5/04 ,  G06F13/1668

    摘要： A memory module includes a module circuit board, an amplifier circuit disposed on the module circuit board for amplifying an input signal, and a memory component to store a data item, wherein the memory component is disposed on the module circuit board. The amplifier circuit includes an input to receive a data signal and an output to provide an amplified data signal. The memory component comprises an input to receive the amplified data signal, wherein the data item is stored in the memory component in dependence on a level of the received amplified data signal.

    摘要翻译： 存储模块包括模块电路板，设置在模块电路板上用于放大输入信号的放大器电路，以及用于存储数据项的存储器组件，其中存储器组件设置在模块电路板上。 放大器电路包括用于接收数据信号的输入端和用于提供放大数据信号的输出端。 存储器组件包括用于接收放大数据信号的输入，其中根据所接收的放大数据信号的电平将数据项存储在存储器组件中。

    Semiconductor memory module
    2.
    发明授权
    Semiconductor memory module 有权
    半导体存储器模块

    公开(公告)号：US07078793B2

    公开(公告)日：2006-07-18

    申请号：US10927312

    申请日：2004-08-27

    申请人： Hermann Ruckerbauer ,  Srdjan Djordjevic

    发明人： Hermann Ruckerbauer ,  Srdjan Djordjevic

    IPC分类号： H01L23/02

    CPC分类号： G11C5/063

    摘要： A semiconductor memory module includes a wiring board in or on which at least a number of data line runs are conducted in a respective width of k bits and which exhibits a number of memory ranks which in each case have n memory chips, and at least one signal driver/control chip (hub), a k-bit-wide data line run in each case connecting a memory chip from each memory rank to the signal driver/control chip (hub) and four or eight memory ranks in each case being arranged distributed on the top and bottom of the wiring board along the associated data line run in such a manner that, in operation, the load is distributed along the respective data line run.

    摘要翻译： 半导体存储器模块包括布线板，其中至少多个数据线运行在k位的相应宽度上，并且具有多个存储器排列，每个存储器级别在每种情况下具有n个存储器芯片，并且至少一个 信号驱动器/控制芯片（集线器），在每种情况下将存储器芯片从每个存储器级连接到信号驱动器/控制芯片（集线器）的k位宽数据线和每个情况下的四个或八个存储器排列被布置 沿着相关联的数据线分布在布线板的顶部和底部，以这样的方式运行：在操作中，负载沿着相应的数据线运行分布。

    Semiconductor memory module
    3.
    发明申请
    Semiconductor memory module 有权
    半导体存储器模块

    公开(公告)号：US20050047250A1

    公开(公告)日：2005-03-03

    申请号：US10927312

    申请日：2004-08-27

    申请人： Hermann Ruckerbauer ,  Srdjan Djordjevic

    发明人： Hermann Ruckerbauer ,  Srdjan Djordjevic

    IPC分类号： G11C5/06 ,  G11C5/00

    CPC分类号： G11C5/063

    摘要： A semiconductor memory module includes a wiring board in or on which at least a number of data line runs are conducted in a respective width of k bits and which exhibits a number of memory ranks which in each case have n memory chips, and at least one signal driver/control chip (hub), a k-bit-wide data line run in each case connecting a memory chip from each memory rank to the signal driver/control chip (hub) and four or eight memory ranks in each case being arranged distributed on the top and bottom of the wiring board along the associated data line run in such a manner that, in operation, the load is distributed along the respective data line run.

    摘要翻译： 半导体存储器模块包括布线板，其中至少多个数据线运行在k位的相应宽度上，并且具有多个存储器排列，每个存储器级别在每种情况下具有n个存储器芯片，并且至少一个 信号驱动器/控制芯片（集线器），在每种情况下将每个存储器级别的存储器芯片连接到信号驱动器/控制芯片（集线器）的k位宽数据线和每个情况下的四个或八个存储器排列 沿着相关联的数据线分布在布线板的顶部和底部，以这样的方式运行：在操作中，负载沿着相应的数据线运行分布。

    Method and apparatus for storage device with a logic unit and method for manufacturing same
    7.
    发明授权
    Method and apparatus for storage device with a logic unit and method for manufacturing same 有权
    具有逻辑单元的存储装置的方法和装置及其制造方法

    公开(公告)号：US07920433B2

    公开(公告)日：2011-04-05

    申请号：US11971819

    申请日：2008-01-09

    申请人： Christoph Bilger ,  Peter Gregorius ,  Michael Bruennert ,  Maurizio Skerlj ,  Wolfgang Walthes ,  Johannes Stecker ,  Hermann Ruckerbauer ,  Dirk Scheideler ,  Roland Barth

    发明人： Christoph Bilger ,  Peter Gregorius ,  Michael Bruennert ,  Maurizio Skerlj ,  Wolfgang Walthes ,  Johannes Stecker ,  Hermann Ruckerbauer ,  Dirk Scheideler ,  Roland Barth

    IPC分类号： G11C7/06

    CPC分类号： G11C7/1006

    摘要： Method and apparatus that relate to a storage device comprising a plurality of memory cells, an interface device configured to connect the storage device to a host system and configured to transmit signals to read and write data from the host system to the memory cells via a first and second data path, and a logic unit. The logic unit is configured to read and write data from the plurality of memory cells via the second data path, and configured to perform logic operations on data stored in the plurality of memory cells. When performing read and write operations, the first data path excludes the logic unit, and the second data path includes the logic unit. Furthermore, the logic unit is communicatively coupled between the interface device and the plurality of memory cells. Additionally, a method for manufacturing the memory device is provided.

    摘要翻译： 涉及包括多个存储器单元的存储设备的方法和装置，接口设备，被配置为将存储设备连接到主机系统，并且被配置为经由第一个存储器单元将数据从主机系统读取和写入到存储器单元 和第二数据路径，以及逻辑单元。 逻辑单元被配置为经由第二数据路径从多个存储器单元读取和写入数据，并且被配置为对存储在多个存储器单元中的数据执行逻辑运算。 当执行读和写操作时，第一数据路径排除逻辑单元，第二数据路径包括逻辑单元。 此外，逻辑单元通信地耦合在接口设备和多个存储器单元之间。 另外，提供了一种用于制造存储器件的方法。

    Stacking Technique for Circuit Devices
    8.
    发明申请
    Stacking Technique for Circuit Devices 审中-公开
    电路器件堆叠技术

    公开(公告)号：US20110034045A1

    公开(公告)日：2011-02-10

    申请号：US12536854

    申请日：2009-08-06

    申请人： Christoph Bilger ,  Peter Gregorius ,  Michael Bruennert ,  Maurizio Skerlj ,  Wolfgang Walthes ,  Johannes Stecker ,  Hermann Ruckerbauer ,  Dirk Scheideler ,  Roland Barth

    发明人： Christoph Bilger ,  Peter Gregorius ,  Michael Bruennert ,  Maurizio Skerlj ,  Wolfgang Walthes ,  Johannes Stecker ,  Hermann Ruckerbauer ,  Dirk Scheideler ,  Roland Barth

    IPC分类号： H01R12/00 ,  H05K1/00

    CPC分类号： H01R31/06 ,  H01L25/105 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2225/1094 ,  H01R12/714 ,  H01R13/2421

    摘要： Stackable circuit devices include mechanical and electrical connection elements that are optionally disengageable and disconnectable. The mechanical connection elements comprise pairs of complementary male and female plug-in engagement elements respectively arranged at opposite matching positions on top and bottom faces of each device package. The male and female plug-in engagement elements provide a mutual plug-in engagement. The electrical connection elements comprise a plurality of first and second complementary contact elements respectively arranged in opposite and matching positions on either the top or bottom face of each device package. When the circuit devices are stacked, the first contact elements are respectively configured to provide an electrical connection to a complementary matching second contact element of an adjacently plugged in circuit device. Some of the stackable circuit devices may accommodate an integrated memory die or chip and others of the stackable circuit devices may include line routing and distribution blocks.

    摘要翻译： 可堆叠电路器件包括机械和电连接元件，其可任选地可分离和可断开。 机械连接元件包括分别布置在每个器件封装的顶面和底面上的相对匹配位置的成对的互补的凸形和阴插入接合元件。 男性和女性插入式接合元件提供相互插件接合。 电连接元件包括多个第一和第二互补触点元件，其分别布置在每个器件封装的顶面或底面上的相对位置和匹配位置。 当电路器件堆叠时，第一接触元件分别构造成提供与相邻插入电路器件的互补匹配的第二接触元件的电连接。 可堆叠电路设备中的一些可以容纳集成存储器管芯或芯片，并且可堆叠电路器件中的其他可以包括线路布线和分配块。

    METHOD FOR CONTROLLING A MEMORY MODULE AND MEMORY CONTROL UNIT
    9.
    发明申请
    METHOD FOR CONTROLLING A MEMORY MODULE AND MEMORY CONTROL UNIT 审中-公开
    用于控制存储器模块和存储器控制单元的方法

    公开(公告)号：US20090287957A1

    公开(公告)日：2009-11-19

    申请号：US12122300

    申请日：2008-05-16

    申请人： Christoph Bilger ,  Peter Gregorius ,  Michael Bruennert ,  Maurizio Skerlj ,  Wolfgang Walthes ,  Johannes Stecker ,  Hermann Ruckerbauer ,  Dirk Scheideler

    发明人： Christoph Bilger ,  Peter Gregorius ,  Michael Bruennert ,  Maurizio Skerlj ,  Wolfgang Walthes ,  Johannes Stecker ,  Hermann Ruckerbauer ,  Dirk Scheideler

    IPC分类号： G06F11/20

    CPC分类号： G11C29/70 ,  G11C5/04

    摘要： A memory control unit for controlling a memory module comprising a plurality of memory cells, said memory control unit comprising means for detecting failure of at least one memory cell, means for deactivating said at least one defective memory cell, means for assigning the address of said at least one defective memory cell to at least one replacement memory cell, first tracking means for tracking the remaining replacement memory cells and masking means to hide the address of a defective memory cell to prevent further usage of this address instead of assigning said address to a replacement memory cell.

    摘要翻译： 一种用于控制包括多个存储单元的存储器模块的存储器控​​制单元，所述存储器控制单元包括用于检测至少一个存储单元的故障的装置，用于停用所述至少一个有缺陷的存储器单元的装置，用于分配所述至少一个存储单元的地址的装置 至少一个有缺陷的存储器单元到至少一个替换存储器单元，用于跟踪剩余的替换存储器单元的第一跟踪装置和隐藏缺陷存储器单元的地址的掩蔽装置，以防止进一步使用该地址而不是将所述地址分配给 更换记忆体。