公开(公告)号：US07541613B2

公开(公告)日：2009-06-02

申请号：US12117014

申请日：2008-05-08

申请人： Brent Alan Anderson ,  Shahid Ahmad Butt ,  Allen H. Gabor ,  Patrick Edward Lindo ,  Edward Joseph Nowak ,  Jed Hickory Rankin

发明人： Brent Alan Anderson ,  Shahid Ahmad Butt ,  Allen H. Gabor ,  Patrick Edward Lindo ,  Edward Joseph Nowak ,  Jed Hickory Rankin

IPC分类号： H01L23/58 ,  H01L21/66 ,  H01L21/00

CPC分类号： H01L22/20

摘要： A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measuring a test device parameter of test devices distributed in different regions; and on a second wafer having the first arrangement of IC chips and the second arrangement of regions, adjusting a functional device parameter of identically designed field effect transistors within one or more regions of all IC chips of the second wafer based on a values of the test device parameter measured on test devices in regions of the IC chip of the first wafer by a non-uniform adjustment of physical or metallurgical polysilicon gate widths of the identically designed field effect transistors from region to region within each IC chip.

摘要翻译： 一种降低参数变化减小的集成电路（IC）芯片和IC芯片的参数变化的方法。 该方法包括：在具有第一芯片布置的第一晶片上，将每个IC芯片分成第二区域布置，测量分布在不同区域中的测试装置的测试装置参数; 并且在具有IC芯片的第一布置和第二区域布置的第二晶片上，基于测试值调整第二晶片的所有IC芯片的一个或多个区域内相同设计的场效应晶体管的功能器件参数 在第一晶片的IC芯片的区域中的测试装置上测量的器件参数通过在每个IC芯片内的区域到区域的相同设计的场效应晶体管的物理或冶金多晶硅栅极宽度的不均匀调整而不均匀地调整。

公开(公告)号：US20090124069A1

公开(公告)日：2009-05-14

申请号：US11939578

申请日：2007-11-14

申请人： William F. Clark, JR. ,  Edward Joseph Nowak

发明人： William F. Clark, JR. ,  Edward Joseph Nowak

IPC分类号： H01L21/265

CPC分类号： H01L21/26586 ,  H01L21/823431 ,  H01L29/105 ,  H01L29/66795 ,  H01L29/66803

摘要： A method for forming a semiconductor structure. The method includes providing a semiconductor structure including a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top substrate surface and (ii) a semiconductor body region. The method further includes implanting an adjustment dose of dopants of a first doping polarity into the semiconductor body region by an adjustment implantation process. Ion bombardment of the adjustment implantation process is in the reference direction. The method further includes (i) patterning the semiconductor substrate resulting in side walls of the semiconductor body region being exposed to a surrounding ambient and then (ii) implanting a base dose of dopants of a second doping polarity into the semiconductor body region by a base implantation process. Ion bombardment of the base implantation process is in a direction which makes a non-zero angle with the reference direction.

摘要翻译： 一种形成半导体结构的方法。 该方法包括提供包括半导体衬底的半导体结构。 半导体衬底包括（i）限定垂直于顶部衬底表面的参考方向的顶部衬底表面和（ii）半导体本体区域。 该方法还包括通过调整注入工艺将第一掺杂极性的掺杂剂的调整剂量注入到半导体体区域中。 离子轰击调整植入过程在参考方向。 该方法还包括（i）对半导体衬底进行图形化，导致半导体体区域的侧壁暴露于周围环境，然后（ii）将碱性剂量的第二掺杂极性掺杂剂注入到半导体本体区域中， 植入过程。 基极注入工艺的离子轰击在与参考方向成非零角度的方向上。

公开(公告)号：US20080296707A1

公开(公告)日：2008-12-04

申请号：US12189298

申请日：2008-08-11

申请人： Brent Alan Anderson ,  Victor W.C. Chan ,  Edward Joseph Nowak

发明人： Brent Alan Anderson ,  Victor W.C. Chan ,  Edward Joseph Nowak

IPC分类号： H01L29/00

CPC分类号： H01L29/66477 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/28518 ,  H01L29/1083 ,  H01L29/42376 ,  H01L29/66507 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654

摘要： A semiconductor transistor with an expanded top portion of a gate and a method for forming the same. The semiconductor transistor with an expanded top portion of a gate includes (a) a semiconductor region which includes a channel region and first and second source/drain regions; the channel region is disposed between the first and second source/drain regions, (b) a gate dielectric region in direct physical contact with the channel region, and (c) a gate electrode region which includes a top portion and a bottom portion. The bottom portion is in direct physical contact with the gate dielectric region. A first width of the top portion is greater than a second width of the bottom portion. The gate electrode region is electrically insulated from the channel region by the gate dielectric region.

摘要翻译： 具有扩大的栅极顶部的半导体晶体管及其形成方法。 具有扩大的栅极顶部的半导体晶体管包括：（a）包括沟道区和第一和第二源极/漏极区的半导体区; 沟道区域设置在第一和第二源极/漏极区域之间，（b）与沟道区域直接物理接触的栅极电介质区域，以及（c）包括顶部和底部的栅电极区域。 底部部分与栅极电介质区域直接物理接触。 顶部的第一宽度大于底部的第二宽度。 栅电极区域通过栅极电介质区域与沟道区域电绝缘。

公开(公告)号：US07453281B2

公开(公告)日：2008-11-18

申请号：US11622040

申请日：2007-01-11

申请人： Brent Alan Anderson ,  Edward Joseph Nowak

发明人： Brent Alan Anderson ,  Edward Joseph Nowak

IPC分类号： H03K19/00

CPC分类号： G06F21/75

摘要： An anti-counterfeiting circuit that is incorporated into an authentic integrated circuit (IC) design, which induces a random failure in a counterfeited IC when the counterfeit IC is manufactured from a reverse-engineered authentic IC. The anti-counterfeiting circuit uses two signals of differing frequencies, which activate a disrupt signal when the two signals meet a predetermined failure criteria, for example, equivalent rising edges. The disrupt signal causes a signal gate or similar element within the counterfeited IC to fail, disrupt, or in some way change a designed behavior of the IC. The disrupt signal may be reset so that the failure will occur again when predetermined failure criteria are met. The authentic IC functions according to design because at least one of the elements in the anti-counterfeit circuit is a camouflage circuit, thus, in an authentic IC the anti-counterfeit circuit is not operatively coupled.

摘要翻译： 一种防伪电路，其被并入真正的集成电路（IC）设计中，当假冒IC由逆向工程认证IC制造时，其引起假冒IC中的随机故障。 防伪电路使用两个不同频率的信号，当两个信号满足预定的故障标准（例如等效的上升沿）时，该信号激活中断信号。 该扰乱信号导致伪造IC内的信号门或类似元件故障，中断或以某种方式改变IC的设计行为。 可以复位中断信号，以便在满足预定的故障标准时再次发生故障。 由于防伪电路中的至少一个元件是伪装电路，所以可信赖的IC功能根据设计，因此，在可靠的IC中，防伪电路不可操作地耦合。

公开(公告)号：US07393703B2

公开(公告)日：2008-07-01

申请号：US11382489

申请日：2006-05-10

申请人： Brent Alan Anderson ,  Shahid Ahmad Butt ,  Allen H. Gabor ,  Patrick Edward Lindo ,  Edward Joseph Nowak ,  Jed Hickory Rankin

发明人： Brent Alan Anderson ,  Shahid Ahmad Butt ,  Allen H. Gabor ,  Patrick Edward Lindo ,  Edward Joseph Nowak ,  Jed Hickory Rankin

IPC分类号： G01R31/26 ,  H01L21/00

CPC分类号： H01L22/20

摘要： A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measuring a test device parameter of test devices distributed in different regions; and on a second wafer having the first arrangement of IC chips and the second arrangement of regions, adjusting a functional device parameter of identically designed field effect transistors within one or more regions of all IC chips of the second wafer based on a values of the test device parameter measured on test devices in regions of the IC chip of the first wafer by a non-uniform adjustment of physical or metallurgical polysilicon gate widths of the identically designed field effect transistors from region to region within each IC chip.

摘要翻译： 一种降低参数变化减小的集成电路（IC）芯片和IC芯片的参数变化的方法。 该方法包括：在具有第一芯片布置的第一晶片上，将每个IC芯片分成第二区域布置，测量分布在不同区域中的测试装置的测试装置参数; 并且在具有IC芯片的第一布置和第二区域布置的第二晶片上，基于测试值调整第二晶片的所有IC芯片的一个或多个区域内相同设计的场效应晶体管的功能器件参数 在第一晶片的IC芯片的区域中的测试装置上测量的器件参数通过在每个IC芯片内的区域到区域的相同设计的场效应晶体管的物理或冶金多晶硅栅极宽度的不均匀调整而不均匀地调整。

公开(公告)号：US20080085456A1

公开(公告)日：2008-04-10

申请号：US11538912

申请日：2006-10-05

申请人： Brent Alan Anderson ,  Edward Joseph Nowak

发明人： Brent Alan Anderson ,  Edward Joseph Nowak

IPC分类号： G03C5/00 ,  G06F17/50 ,  G03F1/00

CPC分类号： H01L21/2686 ,  G03F1/50 ,  H01L21/268

摘要： A mask, a method for creating a mask, and a method for irradiating a substrate through use of the mask. Creating the mask establishes the mask by designing the mask, forming the mask, or both designing and forming the mask. Creating the mask includes receiving a specified target transmittance (TS) of the substrate with respect to radiation propagated from a radiation source and transmitted through the mask with spatial selectivity in accordance with a spatially varying transmissivity (TM) of the mask with respect to the radiation. The mask is disposed between the radiation source and the substrate. The mask includes transparent portions and reflective portions distributed within the transparent portions. The first radiation after having passed through the mask is transmitted into the substrate in accordance with a spatially varying reflectance (R) of the substrate such that TM*(1−R) is about equal to TS.

摘要翻译： 掩模，用于产生掩模的方法，以及通过使用掩模照射基板的方法。 创建掩模通过设计掩模，形成掩模或设计和形成掩模来建立掩模。 创建掩模包括相对于从辐射源传播的辐射接收基底的指定目标透射率（T S S S S S S），并且根据空间变化的透射率（T < 掩模相对于辐射的光束。 掩模设置在辐射源和基板之间。 掩模包括分布在透明部分内的透明部分和反射部分。 已经通过掩模的第一辐射根据衬底的空间变化的反射率（R）传输到衬底中，使得T M *（1-R）大约等于T < SUB> S 。

公开(公告)号：US20080070422A1

公开(公告)日：2008-03-20

申请号：US11427419

申请日：2006-06-29

申请人： Brent Alan Anderson ,  Edward Joseph Nowak

发明人： Brent Alan Anderson ,  Edward Joseph Nowak

IPC分类号： H01L21/00

CPC分类号： B23K26/0626 ,  B23K26/0608 ,  H01L21/26513 ,  H01L21/2686

摘要： A method for configuring J electromagnetic radiation sources (J≧2) to serially irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I≧2; J≦I) thereon. Pj denotes a same source-specific normally incident energy flux on each stack from source j. In each of I independent exposure steps, the I stacks are concurrently exposed to radiation from the J sources. Vi and Si respectively denote an actual and target energy flux transmitted into the substrate via stack i in exposure step i (i=1, . . . , I). t(i) and Pt(i) are computed such that: Vi is maximal through deployment of source t(i) as compared with deployment of any other source for i=1, . . . , I; and an error E being a function of |V1−S1|, |V2−S2|, . . . , |VI−SI| is about minimized with respect to Pi (i=1, . . . , I).

摘要翻译： 一种用于配置J电磁辐射源（J> = 2）以串行照射衬底的方法。 每个源具有不同的发射辐射的波长和角分布的功能。 衬底包括基层和I堆叠（I> = 2; J <= I）THEREON。 表示来自源j的每个堆叠上的源特定的正常入射能量通量相同的源。 在I独立暴露步骤中，I堆叠同时暴露于来自J源的辐射。 分别表示曝光步骤i（i = 1，...，I）中经由堆叠i传输到衬底中的实际和目标能量通量。 计算t（i）和P（i），使得：通过部署源t（i），与部署任何其它源相比，V i i i i i = 1， 。 。 ， 一世; 并且误差E是| V 1 -S 1 |，| V 2 -S 2的函数; |，。 。 。 | | | | | | | | | | | 相对于P iI i（i = 1，...，I）是最小的。

公开(公告)号：US07282423B2

公开(公告)日：2007-10-16

申请号：US11005659

申请日：2004-12-07

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Edward Joseph Nowak

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Edward Joseph Nowak

IPC分类号： H01L21/76

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/2807 ,  H01L21/28114 ,  H01L21/28123 ,  H01L29/1045 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/4991 ,  H01L29/7833

摘要： An FET has a T-shaped gate. The FET has a halo diffusion self-aligned to the bottom portion of the T and an extension diffusion self aligned to the top portion. The halo is thereby separated from the extension implant, and this provides significant advantages. The top and bottom portions of the T-shaped gate can be formed of layers of two different materials, such as germanium and silicon. The two layers are patterned together. Then exposed edges of the bottom layer are selectively chemically reacted and the reaction products are etched away to provide the notch. In another embodiment, the gate is formed of a single gate conductor. A metal is conformally deposited along sidewalls, recess etched to expose a top portion of the sidewalls, and heated to form silicide along bottom portions. The silicide is etched to provide the notch.

摘要翻译： FET具有T形门。 FET具有与T的底部自对准的晕圈扩散，并且与顶部自对准的延伸扩散。 因此，光环与延伸植入物分离，这提供了显着的优点。 T形门的顶部和底部可以由两种不同材料的层形成，例如锗和硅。 两层被图案化在一起。 然后，底层的暴露边缘被选择性地化学反应，并且蚀刻掉反应产物以提供凹口。 在另一个实施例中，栅极由单个栅极导体形成。 金属沿着侧壁共形沉积，凹陷蚀刻以暴露侧壁的顶部，并且被加热以沿底部形成硅化物。 蚀刻硅化物以提供凹口。

公开(公告)号：US6022766A

公开(公告)日：2000-02-08

申请号：US797904

申请日：1997-02-10

申请人： Bomy Able Chen ,  Subhash Balakrishna Kulkarni ,  Jerome Brett Lasky ,  Randy William Mann ,  Edward Joseph Nowak ,  Werner Alois Rausch ,  Francis Roger White

发明人： Bomy Able Chen ,  Subhash Balakrishna Kulkarni ,  Jerome Brett Lasky ,  Randy William Mann ,  Edward Joseph Nowak ,  Werner Alois Rausch ,  Francis Roger White

IPC分类号： H01L27/06 ,  H01L27/11 ,  H01L21/00

CPC分类号： H01L27/1108 ,  H01L27/0688 ,  H01L2924/0002

摘要： An improved field effect transistor (FET) structure is disclosed. It comprises a first insulator layer containing at least one primary level stud extending through the layer; an undoped cap oxide layer disposed over the insulator layer and abutting the upper region of each stud; a primary level thin film transistor (TFT) disposed over the undoped cap oxide layer; and a planarized oxide layer disposed over the TFT. Multiple TFT's can be stacked vertically, and connected to other levels of studs and metal interconnection layers. Another embodiment of the invention includes the use of a protective interfacial cap over the surface of tungsten-type studs. The FET structure can serve as a component of a static random access memory (SRAM) cell. Related processes are also disclosed.

摘要翻译： 公开了一种改进的场效应晶体管（FET）结构。 它包括第一绝缘体层，其包含延伸穿过该层的至少一个主级螺柱; 设置在绝缘体层上并与每个螺柱的上部区域邻接的未掺杂的帽氧化物层; 设置在未掺杂的帽氧化物层上的初级级薄膜晶体管（TFT）; 以及设置在TFT上的平坦化氧化物层。 多个TFT可以垂直堆叠，并连接到其他级别的螺柱和金属互连层。 本发明的另一个实施例包括在钨型螺柱的表面上使用保护性界面盖。 FET结构可以用作静态随机存取存储器（SRAM）单元的组件。 还公开了相关过程。