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61.发明授权Butted SOI junction isolation structures and devices and method of fabrication 有权对接SOI结隔离结构和器件及其制造方法公开(公告)号：US08741725B2
公开(公告)日：2014-06-03
申请号：US12943084
申请日：2010-11-10
IPC分类号： H01L29/06
CPC分类号： H01L29/7824 , H01L21/76237 , H01L21/84 , H01L27/1203
摘要： A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.
摘要翻译： 一种结构，一种FET，一种制造该结构和制造该FET的方法。 该结构包括：绝缘体上硅衬底上的掩埋氧化物（BOX）层上的硅层; 所述硅层中的沟槽从所述硅层的顶表面延伸到所述硅层中，所述沟槽不延伸到所述BOX层，所述硅层中的掺杂区域在所述BOX层之间并与所述沟槽的底部邻接， 掺杂到第一掺杂剂浓度的第一掺杂区; 在沟槽的底部掺杂到第二掺杂剂浓度的第一外延层; 在沟槽中的第一外延层上掺杂到第三掺杂剂浓度的第二外延层; 并且其中所述第三掺杂剂浓度大于所述第一和第二掺杂剂浓度，并且所述第一掺杂剂浓度大于所述第二掺杂剂浓度。
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公开(公告)号：US08586966B2
公开(公告)日：2013-11-19
申请号：US13551995
申请日：2012-07-18
IPC分类号： H01L29/06
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y40/00 , H01L21/823412 , H01L27/1203 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696 , Y10S977/938
摘要： A nanowire field effect transistor (FET) device includes a channel region including a silicon nanowire portion having a first distal end extending from the channel region and a second distal end extending from the channel region, the silicon portion is partially surrounded by a gate stack disposed circumferentially around the silicon portion, a source region including the first distal end of the silicon nanowire portion, a drain region including the second distal end of the silicon nanowire portion, a metallic layer disposed on the source region and the drain region, a first conductive member contacting the metallic layer of the source region, and a second conductive member contacting the metallic layer of the drain region.
摘要翻译： 纳米线场效应晶体管（FET）器件包括沟道区域，该沟道区域包括具有从沟道区域延伸的第一远端的硅纳米线部分和从沟道区域延伸的第二远端，硅部分被设置的栅极堆叠部分地包围 围绕硅部分周向地包括包括硅纳米线部分的第一远端的源极区域，包括硅纳米线部分的第二远端的漏极区域，设置在源极区域和漏极区域上的金属层，第一导电 与源极区域的金属层接触的构件和与漏极区域的金属层接触的第二导电构件。
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63.发明申请公开(公告)号：US20130221319A1
公开(公告)日：2013-08-29
申请号：US13405682
申请日：2012-02-27
IPC分类号： H01L29/775 , H01L21/335
CPC分类号： H01L29/66477 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： Non-planar semiconductor devices are provided that include at least one semiconductor nanowire suspended above a semiconductor oxide layer that is present on a first portion of a bulk semiconductor substrate. An end segment of the at least one semiconductor nanowire is attached to a first semiconductor pad region and another end segment of the at least one semiconductor nanowire is attached to a second semiconductor pad region. The first and second pad regions are located above and are in direct contact with a second portion of the bulk semiconductor substrate which is vertically offsets from the first portion. The structure further includes a gate surrounding a central portion of the at least one semiconductor nanowire, a source region located on a first side of the gate, and a drain region located on a second side of the gate which is opposite the first side of the gate.
摘要翻译： 提供非平面半导体器件，其包括悬浮在存在于体半导体衬底的第一部分上的半导体氧化物层上的至少一个半导体纳米线。 所述至少一个半导体纳米线的端部段附接到第一半导体焊盘区域，并且所述至少一个半导体纳米线的另一个端部段附接到第二半导体焊盘区域。 第一和第二焊盘区域位于与第一部分垂直偏移的体半导体衬底的第二部分的上方并直接接触。 所述结构还包括围绕所述至少一个半导体纳米线的中心部分的栅极，位于所述栅极的第一侧上的源极区域和位于所述栅极的与所述栅极的第一侧相对的第二侧上的漏极区域 门。
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公开(公告)号：US20130105894A1
公开(公告)日：2013-05-02
申请号：US13282619
申请日：2011-10-27
申请人： MaryJane Brodsky , Ming Cai , Dechao Guo , William K. Henson , Shreesh Narasimha , Yue Liang , Liyang Song , Yanfeng Wang , Chun-Chen Yeh
发明人： MaryJane Brodsky , Ming Cai , Dechao Guo , William K. Henson , Shreesh Narasimha , Yue Liang , Liyang Song , Yanfeng Wang , Chun-Chen Yeh
CPC分类号： H01L29/66803
摘要： A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.
摘要翻译： 一种结构包括基板; 设置在所述衬底上的晶体管，所述晶体管包括由碳注入的由硅构成的鳍; 以及覆盖限定晶体管的沟道的鳍片的一部分上的栅极电介质层和栅极金属层。 在该结构中，选择鳍内的碳浓度以建立晶体管的期望电压阈值。 还公开了制造FinFET晶体管的方法。 还公开了具有碳注入阱的平面晶体管，其中选择阱内的碳浓度以建立晶体管的期望电压阈值。
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公开(公告)号：US08343781B2
公开(公告)日：2013-01-01
申请号：US12886612
申请日：2010-09-21
CPC分类号： H01L23/544 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： An apparatus and method for electrical mask inspection is disclosed. A scan chain is formed amongst two metal layers and a via layer. One of the three layers is a functional layer under test, and the other two layers are test layers. A resistance measurement of the scan chain is used to determine if a potential defect exists within one of the vias or metal segments comprising the scan chain.
摘要翻译： 公开了一种用于电气掩模检查的装置和方法。 在两个金属层和通孔层之间形成扫描链。 三层之一是被测功能层，另外两层是测试层。 使用扫描链的电阻测量来确定在包括扫描链的通孔或金属段之一内是否存在潜在缺陷。
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公开(公告)号：US20120329217A1
公开(公告)日：2012-12-27
申请号：US13600585
申请日：2012-08-31
IPC分类号： H01L21/336
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/84 , H01L29/0673 , H01L29/42392 , H01L29/4966 , H01L29/513 , H01L29/66439 , H01L29/78696
摘要： A method for forming a nanowire field effect transistor (FET) device including forming a first silicon on insulator (SOI) pad region, a second SOI pad region, a third SOI pad region, a first SOI portion connecting the first SOI pad region to the second SOI pad region, and a second SOI portion connecting the second SOI pad region to the third SOI pad region on a substrate, patterning a first hardmask layer over the second SOI portion, forming a first suspended nanowire over the semiconductor substrate, forming a first gate structure around a portion of the first suspended nanowire, patterning a second hardmask layer over the first gate structure and the first suspended nanowire, removing the first hardmask layer, forming a second suspended nanowire over the semiconductor substrate, forming a second gate structure around a portion of the second suspended nanowire, and removing the second hardmask layer.
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公开(公告)号：US20120280205A1
公开(公告)日：2012-11-08
申请号：US13551995
申请日：2012-07-18
IPC分类号： H01L29/775 , B82Y99/00
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y40/00 , H01L21/823412 , H01L27/1203 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696 , Y10S977/938
摘要： A nanowire field effect transistor (FET) device includes a channel region including a silicon nanowire portion having a first distal end extending from the channel region and a second distal end extending from the channel region, the silicon portion is partially surrounded by a gate stack disposed circumferentially around the silicon portion, a source region including the first distal end of the silicon nanowire portion, a drain region including the second distal end of the silicon nanowire portion, a metallic layer disposed on the source region and the drain region, a first conductive member contacting the metallic layer of the source region, and a second conductive member contacting the metallic layer of the drain region.
摘要翻译： 纳米线场效应晶体管（FET）器件包括沟道区域，该沟道区域包括具有从沟道区域延伸的第一远端的硅纳米线部分和从沟道区域延伸的第二远端，硅部分被设置的栅极堆叠部分地包围 围绕硅部分周向地包括包括硅纳米线部分的第一远端的源极区域，包括硅纳米线部分的第二远端的漏极区域，设置在源极区域和漏极区域上的金属层，第一导电 与源极区域的金属层接触的构件和与漏极区域的金属层接触的第二导电构件。
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68.发明申请BUTTED SOI JUNCTION ISOLATION STRUCTURES AND DEVICES AND METHOD OF FABRICATION 有权所谓的SOI结隔离结构和装置以及制造方法公开(公告)号：US20120112280A1
公开(公告)日：2012-05-10
申请号：US12943084
申请日：2010-11-10
IPC分类号： H01L29/06 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7824 , H01L21/76237 , H01L21/84 , H01L27/1203
摘要： A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.
摘要翻译： 一种结构，一种FET，一种制造该结构和制造该FET的方法。 该结构包括：绝缘体上硅衬底上的掩埋氧化物（BOX）层上的硅层; 所述硅层中的沟槽从所述硅层的顶表面延伸到所述硅层中，所述沟槽不延伸到所述BOX层，所述硅层中的掺杂区域在所述BOX层之间并与所述沟槽的底部邻接， 掺杂到第一掺杂剂浓度的第一掺杂区; 在沟槽的底部掺杂到第二掺杂剂浓度的第一外延层; 在沟槽中的第一外延层上掺杂到第三掺杂剂浓度的第二外延层; 并且其中所述第三掺杂剂浓度大于所述第一和第二掺杂剂浓度，并且所述第一掺杂剂浓度大于所述第二掺杂剂浓度。
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公开(公告)号：US20120068174A1
公开(公告)日：2012-03-22
申请号：US12886612
申请日：2010-09-21
IPC分类号： H01L23/522 , H01L21/66 , H01L21/768
CPC分类号： H01L23/544 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： An apparatus and method for electrical mask inspection is disclosed. A scan chain is formed amongst two metal layers and a via layer. One of the three layers is a functional layer under test, and the other two layers are test layers. A resistance measurement of the scan chain is used to determine if a potential defect exists within one of the vias or metal segments comprising the scan chain.
摘要翻译： 公开了一种用于电气掩模检查的装置和方法。 在两个金属层和通孔层之间形成扫描链。 三层之一是被测功能层，另外两层是测试层。 使用扫描链的电阻测量来确定在包括扫描链的通孔或金属段之一内是否存在潜在缺陷。
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公开(公告)号：US20100330763A1
公开(公告)日：2010-12-30
申请号：US12493549
申请日：2009-06-29
申请人： Gregory G. Freeman , Shreesh Narasimha , Ning Su , Hasan M. Nayfeh , Nivo Rovedo , Werner A. Rausch , Jian Yu
发明人： Gregory G. Freeman , Shreesh Narasimha , Ning Su , Hasan M. Nayfeh , Nivo Rovedo , Werner A. Rausch , Jian Yu
IPC分类号： H01L21/336
CPC分类号： H01L21/823425 , H01L21/26586 , H01L21/823412 , H01L29/66492 , H01L29/66659
摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming at least a first and a second gate-mask stack on top of a semiconductor substrate, wherein the first and second gate-mask stacks include at least, respectively, a first and a second gate conductor of a first and a second transistor and have, respectively, a top surface, a first side, and a second side with the second side being opposite to the first side; performing a first halo implantation from the first side of the first and second gate-mask stacks at a first angle while applying the first gate-mask stack in preventing the first halo implantation from reaching a first source/drain region of the second transistor, wherein the first angle is equal to or larger than a predetermined value; and performing a second halo implantation from the second side of the first and second gate-mask stacks at a second angle, thereby creating halo implant in a second source/drain region of the second transistor, wherein the first and second angles are measured against a normal to the substrate.
摘要翻译： 本发明提供了形成非对称场效应晶体管的方法。 该方法包括在半导体衬底的顶部上形成至少第一和第二栅极掩模叠层，其中第一和第二栅极掩模叠层至少分别包括第一和第二栅极掩模叠层的第一和第二栅极导体 分别具有顶表面，第一侧和第二侧，第二侧与第一侧相对; 以第一角度从第一和第二栅极掩模叠层的第一侧进行第一光晕注入，同时施加第一栅极掩模叠层以防止第一光晕注入到达第二晶体管的第一源极/漏极区域，其中 第一角度等于或大于预定值; 以及以第二角度从所述第一和第二栅极掩模叠层的第二侧执行第二光晕注入，从而在所述第二晶体管的第二源极/漏极区域中产生晕轮注入，其中所述第一和第二角度是针对 与基底垂直。
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