公开(公告)号：US20130105894A1

公开(公告)日：2013-05-02

申请号：US13282619

申请日：2011-10-27

申请人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

发明人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

IPC分类号： H01L27/12 ,  H01L21/04

CPC分类号： H01L29/66803

摘要： A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.

摘要翻译： 一种结构包括基板; 设置在所述衬底上的晶体管，所述晶体管包括由碳注入的由硅构成的鳍; 以及覆盖限定晶体管的沟道的鳍片的一部分上的栅极电介质层和栅极金属层。 在该结构中，选择鳍内的碳浓度以建立晶体管的期望电压阈值。 还公开了制造FinFET晶体管的方法。 还公开了具有碳注入阱的平面晶体管，其中选择阱内的碳浓度以建立晶体管的期望电压阈值。

公开(公告)号：US20130105896A1

公开(公告)日：2013-05-02

申请号：US13625350

申请日：2012-09-24

申请人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

发明人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

IPC分类号： H01L27/12

CPC分类号： H01L29/66803

摘要： A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor.

摘要翻译： 一种结构包括基板; 设置在所述衬底上的晶体管，所述晶体管包括由碳注入的由硅构成的鳍; 以及覆盖限定晶体管的沟道的鳍片的一部分上的栅极电介质层和栅极金属层。 在该结构中，选择鳍内的碳浓度以建立晶体管的期望电压阈值。

公开(公告)号：US09040399B2

公开(公告)日：2015-05-26

申请号：US13282619

申请日：2011-10-27

申请人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

发明人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

IPC分类号： H01L21/425 ,  H01L29/66

CPC分类号： H01L29/66803

摘要： A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.

摘要翻译： 一种结构包括基板; 设置在所述衬底上的晶体管，所述晶体管包括由碳注入的由硅构成的鳍; 以及覆盖限定晶体管的沟道的鳍片的一部分上的栅极电介质层和栅极金属层。 在该结构中，选择鳍内的碳浓度以建立晶体管的期望电压阈值。 还公开了制造FinFET晶体管的方法。 还公开了具有碳注入阱的平面晶体管，其中选择阱内的碳浓度以建立晶体管的期望电压阈值。

公开(公告)号：US08729637B2

公开(公告)日：2014-05-20

申请号：US13253268

申请日：2011-10-05

申请人： Yue Liang ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yanfeng Wang

发明人： Yue Liang ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yanfeng Wang

IPC分类号： H01L21/70 ,  H01L21/20 ,  H01L21/00

CPC分类号： H01L27/092 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/517

摘要： A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×1016 atoms/cm3 to 1×1021 atoms/cm3 is present at an interface between the high-k gate dielectric of the gate structure for the n-type semiconductor device and the semiconductor substrate. Methods of forming the aforementioned device are also disclosed.

摘要翻译： 一种在半导体衬底上包括p型半导体器件和n型半导体器件的器件。 n型半导体器件包括具有高k栅极电介质的栅极结构。 在n型半导体器件的栅极结构的高k栅极电介质和半导体衬底之间的界面处存在浓度范围为1×1016原子/ cm3至1×1021原子/ cm3的碳掺杂剂。 还公开了形成上述装置的方法。

公开(公告)号：US20130087859A1

公开(公告)日：2013-04-11

申请号：US13253268

申请日：2011-10-05

申请人： Yue Liang ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yanfeng Wang

发明人： Yue Liang ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yanfeng Wang

IPC分类号： H01L21/266 ,  H01L27/092

CPC分类号： H01L27/092 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/517

摘要： A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×1016 atoms/cm3 to 1×1021 atoms/cm3 is present at an interface between the high-k gate dielectric of the gate structure for the n-type semiconductor device and the semiconductor substrate. Methods of forming the aforementioned device are also disclosed.

摘要翻译： 一种在半导体衬底上包括p型半导体器件和n型半导体器件的器件。 n型半导体器件包括具有高k栅极电介质的栅极结构。 在n型半导体器件的栅极结构的高k栅极电介质和半导体衬底之间的界面处存在浓度范围为1×1016原子/ cm3至1×1021原子/ cm3的碳掺杂剂。 还公开了形成上述装置的方法。

公开(公告)号：US20130330899A1

公开(公告)日：2013-12-12

申请号：US13527063

申请日：2012-06-19

申请人： Huiming Bu ,  Ming Cai ,  Kevin K. Chan ,  Dechao Guo ,  Ravikumar Ramachandran ,  Liyang Song ,  Chun-Chen Yeh

发明人： Huiming Bu ,  Ming Cai ,  Kevin K. Chan ,  Dechao Guo ,  Ravikumar Ramachandran ,  Liyang Song ,  Chun-Chen Yeh

IPC分类号： H01L21/336 ,  H01L21/04

CPC分类号： H01L29/78 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/665 ,  H01L29/66628

摘要： A method of forming gate stack structure for a transistor device includes forming a gate dielectric layer over a substrate; forming a first silicon gate layer over the gate dielectric layer; forming a dopant-rich monolayer over the first silicon gate layer; and forming a second silicon gate layer over the dopant-rich monolayer, wherein the dopant-rich monolayer prevents silicidation of the first silicon gate layer during silicidation of the second silicon gate layer.

摘要翻译： 一种形成用于晶体管器件的栅叠层结构的方法包括在衬底上形成栅介电层; 在所述栅极介电层上形成第一硅栅极层; 在所述第一硅栅极层上形成富含掺杂剂的单层; 以及在所述富掺杂剂单层上形成第二硅栅极层，其中所述富掺杂剂层在所述第二硅栅极层的硅化期间防止所述第一硅栅极层的硅化。

公开(公告)号：US20130264653A1

公开(公告)日：2013-10-10

申请号：US13443133

申请日：2012-04-10

申请人： Ming Cai ,  Dechao Guo ,  Liyang Song ,  Chun-Chen Yeh

发明人： Ming Cai ,  Dechao Guo ,  Liyang Song ,  Chun-Chen Yeh

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L27/1203 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161

摘要： A method of forming a complementary metal oxide semiconductor (CMOS) device including an n-type field effect transistor (NFET) and an p-type field effect transistor (PFET) having fully silicided gates electrode in which an improved dual stress buried insulator is employed to incorporate and advantageous mechanical stress into the device channel of the NFET and PFET. The method can be imposed on a bulk substrate or extremely thin silicon on insulator (ETSOI) substrate. The device includes a semiconductor substrate, a plurality of shallow trench isolations structures formed in the ETSOI layer, NFET having a source and drain region and a gate formation, a PFET having a source and drain region, and a gate formation, an insulator layer, including a stressed oxide or nitride, deposited inside the substrate of the NFET, and a second insulator layer, including either an stressed oxide or nitride, deposited inside the substrate of the PFET.

公开(公告)号：US20130207194A1

公开(公告)日：2013-08-15

申请号：US13396872

申请日：2012-02-15

申请人： Ming Cai ,  Dechao Guo ,  Liyang Song ,  Chun-Chen Yeh

发明人： Ming Cai ,  Dechao Guo ,  Liyang Song ,  Chun-Chen Yeh

IPC分类号： H01L21/336 ,  H01L27/088

CPC分类号： H01L29/7846 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/845 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78684

摘要： A method for fabricating a transistor with uniaxial stress channels includes depositing an insulating layer onto a substrate, defining bars within the insulating layer, recessing a channel into the substrate, growing a first semiconducting material in the channel, defining a gate stack over the bars and semiconducting material, defining source and drain recesses and embedding a second semiconducting material into the source and drain recesses.

摘要翻译： 用于制造具有单轴应力通道的晶体管的方法包括：将绝缘层沉积到衬底上，在绝缘层内限定棒，将沟道凹入衬底中，在沟道中生长第一半导体材料，在栅柱上限定栅叠层， 半导体材料，限定源极和漏极凹部并且将第二半导体材料嵌入到源极和漏极凹部中。

公开(公告)号：US20130328135A1

公开(公告)日：2013-12-12

申请号：US13494312

申请日：2012-06-12

申请人： Huiming Bu ,  Ming Cai ,  Kevin K. Chan ,  Dechao Guo ,  Ravikumar Ramachandran ,  Liyang Song ,  Chun-Chen Yeh

发明人： Huiming Bu ,  Ming Cai ,  Kevin K. Chan ,  Dechao Guo ,  Ravikumar Ramachandran ,  Liyang Song ,  Chun-Chen Yeh

IPC分类号： H01L29/78

CPC分类号： H01L29/78 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/665 ,  H01L29/66628

摘要： A gate stack structure for a transistor device includes a gate dielectric layer formed over a substrate; a first silicon gate layer formed over the gate dielectric layer; a dopant-rich monolayer formed over the first silicon gate layer; and a second silicon gate layer formed over the dopant-rich monolayer, wherein the dopant-rich monolayer prevents silicidation of the first silicon gate layer during silicidation of the second silicon gate layer.

摘要翻译： 用于晶体管器件的栅极堆叠结构包括形成在衬底上的栅极电介质层; 形成在所述栅极介电层上的第一硅栅极层; 在第一硅栅极层上形成的掺杂剂富含单层; 以及形成在所述富掺杂剂单层上的第二硅栅极层，其中所述富掺杂剂层在所述第二硅栅极层的硅化期间防止所述第一硅栅极层的硅化。

公开(公告)号：US08927364B2

公开(公告)日：2015-01-06

申请号：US13443133

申请日：2012-04-10

申请人： Ming Cai ,  Dechao Guo ,  Liyang Song ,  Chun-Chen Yeh

发明人： Ming Cai ,  Dechao Guo ,  Liyang Song ,  Chun-Chen Yeh

IPC分类号： H01L21/8238

CPC分类号： H01L27/1203 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161

摘要： A method of forming a complementary metal oxide semiconductor (CMOS) device including an n-type field effect transistor (NFET) and an p-type field effect transistor (PFET) having fully silicided gates electrode in which an improved dual stress buried insulator is employed to incorporate and advantageous mechanical stress into the device channel of the NFET and PFET. The method can be imposed on a bulk substrate or extremely thin silicon on insulator (ETSOI) substrate. The device includes a semiconductor substrate, a plurality of shallow trench isolations structures formed in the ETSOI layer, NFET having a source and drain region and a gate formation, a PFET having a source and drain region, and a gate formation, an insulator layer, including a stressed oxide or nitride, deposited inside the substrate of the NFET, and a second insulator layer, including either an stressed oxide or nitride, deposited inside the substrate of the PFET.

摘要翻译： 一种形成具有n型场效应晶体管（NFET）和具有完全硅化栅电极的p型场效应晶体管（PFET）的互补金属氧化物半导体（CMOS）器件的方法，其中采用改进的双重应力掩埋绝缘体 以将NFE和PFET的器件沟道中的机械应力引入和有利。 该方法可以施加在体衬底或极薄的绝缘体上（ETSOI）衬底上。 该器件包括半导体衬底，在ETSOI层中形成的多个浅沟槽隔离结构，具有源极和漏极区域以及栅极形成的NFET，具有源极和漏极区域的PFET以及栅极形成，绝缘体层， 包括沉积在NFET的衬底内的受压氧化物或氮化物，以及沉积在PFET的衬底内的包括应力氧化物或氮化物的第二绝缘体层。