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    THRESHOLD VOLTAGE ADJUSTMENT FOR THIN BODY MOSFETS
    1.
    发明申请
    THRESHOLD VOLTAGE ADJUSTMENT FOR THIN BODY MOSFETS 有权
    用于薄体MOSFET的阈值电压调整

    公开(公告)号：US20130105894A1

    公开(公告)日：2013-05-02

    申请号：US13282619

    申请日：2011-10-27

    申请人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

    发明人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

    IPC分类号： H01L27/12 ,  H01L21/04

    CPC分类号： H01L29/66803

    摘要： A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.

    摘要翻译： 一种结构包括基板; 设置在所述衬底上的晶体管，所述晶体管包括由碳注入的由硅构成的鳍; 以及覆盖限定晶体管的沟道的鳍片的一部分上的栅极电介质层和栅极金属层。 在该结构中，选择鳍内的碳浓度以建立晶体管的期望电压阈值。 还公开了制造FinFET晶体管的方法。 还公开了具有碳注入阱的平面晶体管，其中选择阱内的碳浓度以建立晶体管的期望电压阈值。

    Threshold voltage adjustment for thin body MOSFETs
    3.
    发明授权
    Threshold voltage adjustment for thin body MOSFETs 有权
    薄体MOSFET的阈值电压调整

    公开(公告)号：US09040399B2

    公开(公告)日：2015-05-26

    申请号：US13282619

    申请日：2011-10-27

    申请人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

    发明人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

    IPC分类号： H01L21/425 ,  H01L29/66

    CPC分类号： H01L29/66803

    摘要： A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.

    摘要翻译： 一种结构包括基板; 设置在所述衬底上的晶体管，所述晶体管包括由碳注入的由硅构成的鳍; 以及覆盖限定晶体管的沟道的鳍片的一部分上的栅极电介质层和栅极金属层。 在该结构中，选择鳍内的碳浓度以建立晶体管的期望电压阈值。 还公开了制造FinFET晶体管的方法。 还公开了具有碳注入阱的平面晶体管，其中选择阱内的碳浓度以建立晶体管的期望电压阈值。

    Complementary Metal Oxide Semiconductor (CMOS) Device Having Gate Structures Connected By A Metal Gate Conductor
    6.
    发明申请
    Complementary Metal Oxide Semiconductor (CMOS) Device Having Gate Structures Connected By A Metal Gate Conductor 有权
    互补金属氧化物半导体（CMOS）器件，其栅极结构由金属栅极导体连接

    公开(公告)号：US20130168776A1

    公开(公告)日：2013-07-04

    申请号：US13342435

    申请日：2012-01-03

    申请人： Yue Liang ,  Dureseti Chidambarrao ,  Brian J. Greene ,  William K. Henson ,  Unoh Kwon ,  Shreesh Narasimha ,  Xiaojun Yu

    发明人： Yue Liang ,  Dureseti Chidambarrao ,  Brian J. Greene ,  William K. Henson ,  Unoh Kwon ,  Shreesh Narasimha ,  Xiaojun Yu

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/823871 ,  H01L21/28079 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/4958

    摘要： A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.

    摘要翻译： 一种互补金属氧化物半导体（CMOS）器件，包括包括第一有源区和第二有源区的衬底，其中衬底的第一有源区和第二有源区中的每一个被隔离区彼此分开。 n型半导体器件存在于衬底的第一有源区上，其中n型半导体器件包括栅极结构的第一部分。 p型半导体器件存在于衬底的第二有源区上，其中p型半导体器件包括栅极结构的第二部分。 连接栅极部分提供栅极结构的第一部分和栅极结构的第二部分之间的电连接。 与连接栅极部分的电接触超过隔离区域，并且不在第一有源区域和/或第二有源区域之上。

    Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor
    7.
    发明授权
    Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor 有权
    具有通过金属栅极导体连接的栅极结构的互补金属氧化物半导体（CMOS）器件

    公开(公告)号：US08803243B2

    公开(公告)日：2014-08-12

    申请号：US13342435

    申请日：2012-01-03

    申请人： Yue Liang ,  Dureseti Chidambarrao ,  Brian J. Greene ,  William K. Henson ,  Unoh Kwon ,  Shreesh Narasimha ,  Xiaojun Yu

    发明人： Yue Liang ,  Dureseti Chidambarrao ,  Brian J. Greene ,  William K. Henson ,  Unoh Kwon ,  Shreesh Narasimha ,  Xiaojun Yu

    IPC分类号： H01L21/70

    CPC分类号： H01L21/823871 ,  H01L21/28079 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/4958

    摘要： A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.

    摘要翻译： 一种互补金属氧化物半导体（CMOS）器件，包括包括第一有源区和第二有源区的衬底，其中衬底的第一有源区和第二有源区中的每一个被隔离区彼此分开。 n型半导体器件存在于衬底的第一有源区上，其中n型半导体器件包括栅极结构的第一部分。 p型半导体器件存在于衬底的第二有源区上，其中p型半导体器件包括栅极结构的第二部分。 连接栅极部分提供栅极结构的第一部分和栅极结构的第二部分之间的电连接。 与连接栅极部分的电接触超过隔离区域，并且不在第一有源区域和/或第二有源区域之上。

    Semiconductor structure for low parasitic gate capacitance
    9.
    发明授权
    Semiconductor structure for low parasitic gate capacitance 有权
    用于低寄生栅极电容的半导体结构

    公开(公告)号：US07709910B2

    公开(公告)日：2010-05-04

    申请号：US11738666

    申请日：2007-04-23

    申请人： William K. Henson ,  Paul Chung-Muh Chang ,  Dureseti Chidambarrao ,  Ricardo A. Donaton ,  Yaocheng Liu ,  Shreesh Narasimha ,  Amanda L. Tessier

    发明人： William K. Henson ,  Paul Chung-Muh Chang ,  Dureseti Chidambarrao ,  Ricardo A. Donaton ,  Yaocheng Liu ,  Shreesh Narasimha ,  Amanda L. Tessier

    IPC分类号： H01L29/78

    CPC分类号： H01L21/823807 ,  H01L21/28097 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76844 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7843

    摘要： A semiconductor structure provides lower parasitic capacitance between the gate electrode and contact vias while providing substantially the same level of stress applied by a nitride liner as conventional MOSFETs by reducing the height of the gate electrode and maintaining substantially the same height for the gate spacer. The nitride liner contacts only the outer sidewalls of the gate spacer, while not contacting inner sidewalls, or only a small area of the inner sidewalls of the gate spacer, therefore applying substantially the same level of stress to the channel of the MOSFET as conventional MOSFETs. The volume surrounded by the gate spacer and located above the gate electrode is either filled with a low-k dielectric material or occupied by a cavity having a dielectric constant of substantially 1.0. The reduced height of the gate electrode and the low-k dielectric gate filler or the cavity reduces the parasitic capacitance.

    摘要翻译： 半导体结构在栅电极和接触通孔之间提供较低的寄生电容，同时通过降低栅极电极的高度并保持与栅极间隔件基本上相同的高度，提供与常规MOSFET相同的氮化物衬垫施加的基本相同的应力水平。 氮化物衬垫仅接触栅极间隔物的外侧壁，而不接触内侧壁，或者仅接触栅极隔离物的内侧壁的小面积，因此与常规MOSFET相比施加与MOSFET的通道基本相同的应力水平 。 由栅极间隔物围绕并位于栅极电极上方的体积填充有低k电介质材料或由具有基本上1.0的介电常数的空腔占据。 栅电极和低k电介质栅极填充物或空腔的降低的高度减小了寄生电容。