利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

45 条记录 (耗时 0.04 秒)

    THRESHOLD VOLTAGE ADJUSTMENT FOR THIN BODY MOSFETS
    1.
    发明申请
    THRESHOLD VOLTAGE ADJUSTMENT FOR THIN BODY MOSFETS 有权
    用于薄体MOSFET的阈值电压调整

    公开(公告)号：US20130105894A1

    公开(公告)日：2013-05-02

    申请号：US13282619

    申请日：2011-10-27

    申请人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

    发明人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

    IPC分类号： H01L27/12 ,  H01L21/04

    CPC分类号： H01L29/66803

    摘要： A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.

    摘要翻译： 一种结构包括基板; 设置在所述衬底上的晶体管，所述晶体管包括由碳注入的由硅构成的鳍; 以及覆盖限定晶体管的沟道的鳍片的一部分上的栅极电介质层和栅极金属层。 在该结构中，选择鳍内的碳浓度以建立晶体管的期望电压阈值。 还公开了制造FinFET晶体管的方法。 还公开了具有碳注入阱的平面晶体管，其中选择阱内的碳浓度以建立晶体管的期望电压阈值。

    Threshold voltage adjustment for thin body MOSFETs
    3.
    发明授权
    Threshold voltage adjustment for thin body MOSFETs 有权
    薄体MOSFET的阈值电压调整

    公开(公告)号：US09040399B2

    公开(公告)日：2015-05-26

    申请号：US13282619

    申请日：2011-10-27

    申请人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

    发明人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

    IPC分类号： H01L21/425 ,  H01L29/66

    CPC分类号： H01L29/66803

    摘要： A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.

    摘要翻译： 一种结构包括基板; 设置在所述衬底上的晶体管，所述晶体管包括由碳注入的由硅构成的鳍; 以及覆盖限定晶体管的沟道的鳍片的一部分上的栅极电介质层和栅极金属层。 在该结构中，选择鳍内的碳浓度以建立晶体管的期望电压阈值。 还公开了制造FinFET晶体管的方法。 还公开了具有碳注入阱的平面晶体管，其中选择阱内的碳浓度以建立晶体管的期望电压阈值。

    Structure and method of high-performance extremely thin silicon on insulator complementary metal—oxide—semiconductor transistors with dual stress buried insulators
    8.
    发明授权
    Structure and method of high-performance extremely thin silicon on insulator complementary metal—oxide—semiconductor transistors with dual stress buried insulators 有权
    具有双应力埋层绝缘体的高性能极薄硅绝缘体互补金属氧化物半导体晶体管的结构和方法

    公开(公告)号：US08927364B2

    公开(公告)日：2015-01-06

    申请号：US13443133

    申请日：2012-04-10

    申请人： Ming Cai ,  Dechao Guo ,  Liyang Song ,  Chun-Chen Yeh

    发明人： Ming Cai ,  Dechao Guo ,  Liyang Song ,  Chun-Chen Yeh

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/1203 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161

    摘要： A method of forming a complementary metal oxide semiconductor (CMOS) device including an n-type field effect transistor (NFET) and an p-type field effect transistor (PFET) having fully silicided gates electrode in which an improved dual stress buried insulator is employed to incorporate and advantageous mechanical stress into the device channel of the NFET and PFET. The method can be imposed on a bulk substrate or extremely thin silicon on insulator (ETSOI) substrate. The device includes a semiconductor substrate, a plurality of shallow trench isolations structures formed in the ETSOI layer, NFET having a source and drain region and a gate formation, a PFET having a source and drain region, and a gate formation, an insulator layer, including a stressed oxide or nitride, deposited inside the substrate of the NFET, and a second insulator layer, including either an stressed oxide or nitride, deposited inside the substrate of the PFET.

    摘要翻译： 一种形成具有n型场效应晶体管（NFET）和具有完全硅化栅电极的p型场效应晶体管（PFET）的互补金属氧化物半导体（CMOS）器件的方法，其中采用改进的双重应力掩埋绝缘体 以将NFE和PFET的器件沟道中的机械应力引入和有利。 该方法可以施加在体衬底或极薄的绝缘体上（ETSOI）衬底上。 该器件包括半导体衬底，在ETSOI层中形成的多个浅沟槽隔离结构，具有源极和漏极区域以及栅极形成的NFET，具有源极和漏极区域的PFET以及栅极形成，绝缘体层， 包括沉积在NFET的衬底内的受压氧化物或氮化物，以及沉积在PFET的衬底内的包括应力氧化物或氮化物的第二绝缘体层。

    Embedded stressors for multigate transistor devices
    10.
    发明授权
    Embedded stressors for multigate transistor devices 有权
    多晶硅晶体管器件的嵌入式应力

    公开(公告)号：US08659091B2

    公开(公告)日：2014-02-25

    申请号：US13611068

    申请日：2012-09-12

    申请人： Ming Cai ,  Dechao Guo ,  Pranita Kulkarni ,  Chun-Chen Yeh

    发明人： Ming Cai ,  Dechao Guo ,  Pranita Kulkarni ,  Chun-Chen Yeh

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66795 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/785

    摘要： Multigate transistor devices and methods of their fabrication are disclosed. In accordance with one method, a fin and a gate structure that is disposed on a plurality of surfaces of the fin are formed. In addition, at least a portion of an extension of the fin is removed to form a recessed portion that is below the gate structure, is below a channel region of the fin, and includes at least one angled indentation. Further, a terminal extension is grown in the at least one angled indentation below the channel region and along a surface of the channel region such that the terminal extension provides a stress on the channel region to enhance charge carrier mobility in the channel region.

    摘要翻译： 公开了多晶体管器件及其制造方法。 根据一种方法，形成设置在翅片的多个表面上的翅片和栅极结构。 此外，除去翅片的延伸部的至少一部分以形成位于栅极结构下方的凹陷部分，在鳍的沟道区域下方，并且包括至少一个成角度的凹陷。 此外，端子延伸在通道区域下方并且沿着沟道区域的表面的至少一个成角度的凹陷中生长，使得端子延伸部在沟道区域上提供应力以增强沟道区域中的载流子迁移率。