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    Devices and Methods for Controlling Write Operations
    61.
    发明申请
    Devices and Methods for Controlling Write Operations 有权

    公开(公告)号：US20210090653A1

    公开(公告)日：2021-03-25

    申请号：US16582743

    申请日：2019-09-25

    Applicant: Arm Limited

    Inventor： Fernando Garcia Redondo ,  Shidhartha Das ,  Glen Arnold Rosendale ,  George McNeil Lattimore ,  Mudit Bhargava

    IPC: G11C13/00

    Abstract: In a particular implementation, a method includes: providing a first voltage to a word-line coupled to a first transistor device; providing a second voltage to a bit-line coupled to the first transistor device; providing a third voltage to a source-line coupled between a programmable resistive device and a voltage control element. Also, the first transistor device is coupled to the programmable resistive device and the voltage control element, where the programmable resistive device is configured to replace a first data value by writing a second data value in the programmable resistive device. Moreover, in response to a voltage difference across the programmable resistive device exceeding a particular threshold, limiting the voltage difference by one of reducing the second voltage on the bit-line or increasing the third voltage on the source-line.

    DIELET DESIGN TECHNIQUES
    62.
    发明申请
    DIELET DESIGN TECHNIQUES 有权

    公开(公告)号：US20210081508A1

    公开(公告)日：2021-03-18

    申请号：US16569482

    申请日：2019-09-12

    Applicant: Arm Limited

    Inventor： Xiaoqing Xu ,  Brian Tracy Cline ,  Saurabh Pijuskumar Sinha ,  Stephen Lewis Moore ,  Mudit Bhargava

    IPC: G06F17/50

    Abstract: Various implementations described herein are directed to an integrated circuit (IC) having a design that is severable into multiple sub-circuits having input-output (IO) ports. The integrated circuit (IC) may include multiple physical electrical connections that are adapted to electrically interconnect the IO ports of the multiple sub-circuits to operate as the IC, and the IO ports have three-dimensional (3D) geometric position information associated therewith.

    Method and apparatus for memory wear leveling
    63.
    发明授权
    Method and apparatus for memory wear leveling 有权

    公开(公告)号：US10761976B2

    公开(公告)日：2020-09-01

    申请号：US15361804

    申请日：2016-11-28

    Applicant: ARM Limited

    Inventor： Mudit Bhargava ,  Joel Thornton Irby ,  Vikas Chandra

    IPC: H04L9/08 ,  G06F12/02 ,  G11C13/00

    Abstract: A method and apparatus is provided for wear leveling of a storage medium in an electronic device. Wear leveling is achieved by mapping each logical memory address to a corresponding physical memory address. The mapping information is consistent over an on-period of a power cycle, but changes from one power cycle to another. The mapping information, such as a key value for example, may be stored in non-volatile memory such as, for example, a correlated electron random switch (CES) storage element. The mapping may be obtained by manipulating bits of the logical address to obtain the physical address.

    Logic encryption using on-chip memory cells
    67.
    发明授权
    Logic encryption using on-chip memory cells 有权

    公开(公告)号：US10438022B2

    公开(公告)日：2019-10-08

    申请号：US15381222

    申请日：2016-12-16

    Applicant: ARM Limited

    Inventor： Vikas Chandra ,  Mudit Bhargava

    IPC: G06F21/00 ,  G06F21/72 ,  H04L9/00 ,  H04L9/06 ,  G06F21/75 ,  G06F21/76 ,  H03K19/177 ,  G09C1/06

    Abstract: A protected circuit includes a logic circuit having one or more input nodes and one or more output nodes. The logic circuit has a network of logic elements and one or more logic encryption elements. A logic encryption element includes a memory cell, such as a correlated electron switch for example, coupled with a configurable sub-circuit that is configured by a value stored in the memory cell to encrypt a signal or a signal path. A mapping of values at the one or more input nodes to values at the one or more output nodes corresponds to a desired mapping when values stored in the one or more memory cells match component values of a prescribed key vector. The memory cells may be programmed after fabrication of the circuit.

    Fast quasi-parity checker for correlated electron switch (CES) memory array
    68.
    发明授权
    Fast quasi-parity checker for correlated electron switch (CES) memory array 有权

    公开(公告)号：US09953726B1

    公开(公告)日：2018-04-24

    申请号：US15361789

    申请日：2016-11-28

    Applicant: ARM Limited

    Inventor： Joel Thornton Irby ,  Mudit Bhargava

    IPC: G11C7/00 ,  G11C29/50 ,  G11C13/00

    CPC classification number: G11C29/50008 ,  G11C13/0002 ,  G11C13/0069 ,  G11C13/0097

    Abstract: An apparatus is provided for testing storage elements that include a variable impedance element switchable between a first impedance state and a second impedance state. The apparatus includes an interconnect circuit for coupling storage elements in a selected arrangement. The apparatus includes an impedance sensing circuit operable to measure at least a resistive component of an impedance of the coupled storage elements and a test controller operable to configure the interconnect circuit and initiate measurement of the combined impedance of the coupled storage elements by the impedance sensing circuit. The impedance sensing circuit compares the measured impedance with at least a resistive component of an expected impedance. The storage elements and apparatus may form part of an integrated circuit. A storage element may include a correlated electron switch, for example.

    Fast memory array repair using local correlated electron switch (CES) memory cells
    69.
    发明授权
    Fast memory array repair using local correlated electron switch (CES) memory cells 有权

    公开(公告)号：US09767924B1

    公开(公告)日：2017-09-19

    申请号：US15381415

    申请日：2016-12-16

    Applicant: ARM Limited

    Inventor： Mudit Bhargava ,  Joel Thornton Irby

    IPC: G11C29/26 ,  G11C29/00 ,  G11C8/10

    CPC classification number: G11C29/76 ,  G11C29/028 ,  G11C29/4401 ,  G11C29/50

    Abstract: An integrated circuit is provided for self-repair of a memory array. The circuit includes first word lines coupled to first memory rows of the memory array, one first word line for each bit of a line address word, second word lines coupled to one or more spare memory rows of the memory array. Repair configuration data is stored in memory cells within the integrated circuit to direct memory accesses to spare memory rows rather than dysfunctional first memory rows. A memory cell may be based on a correlated electron switch (CES). A built-in self-test circuit is provided to facilitate setting of repair configuration data. The repair data may be reconfigurable, enabling operating margins to be improved by testing under various operating conditions.

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