公开(公告)号：US11316003B2

公开(公告)日：2022-04-26

申请号：US16959010

申请日：2020-02-25

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xue Dong ,  Guangcai Yuan ,  Haixu Li ,  Zhanfeng Cao ,  Ke Wang ,  Zhijun Lv ,  Fei Wang ,  Huijuan Wang ,  Zhiwei Liang ,  Xinhong Lu

IPC: H01L27/32

Abstract: Disclosed are an array substrate, and a display device, and a method for manufacturing the same. The array substrate includes: a base substrate, and a thin film transistor, a planarization pattern, a bonding pattern, and a conductive structure that are disposed on the base substrate. The thin film transistor, the planarization pattern, and the bonding pattern are laminated in a direction going distally from the base substrate. The planarization pattern is provided with a via and a groove, the conductive structure is disposed in the via, wherein the bonding pattern is conductive and is electrically connected to the thin film transistor by the conductive structure, an orthographic projection of the bonding pattern on the base substrate falls outside an orthographic projection of the groove on the base substrate, and the groove is configured to accommodate an adhesive.

公开(公告)号：US11257852B2

公开(公告)日：2022-02-22

申请号：US16966146

申请日：2019-12-25

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Haixu Li ,  Zhanfeng Cao ,  Ke Wang

IPC: H01L27/12 ,  H01L25/16 ,  H01L33/62 ,  H01L23/00

Abstract: A circuit backplane of a display panel, a method for manufacturing the same, and a display panel are provided. The circuit backplane includes a substrate and a plurality of circuit regions on the substrate. Each of the plurality of circuit regions includes a cathode soldered electrode, an anode soldered electrode, and a flow blocking island that are on the substrate. The flow blocking island is between the cathode soldered electrode and the anode soldered electrode, and in a thickness direction of the circuit backplane, a height of the flow blocking island is greater than each of a height of the cathode soldered electrode and a height of the anode soldered electrode.

公开(公告)号：US11244966B2

公开(公告)日：2022-02-08

申请号：US16682395

申请日：2019-11-13

Applicant: BOE Technology Group Co., Ltd.

Inventor： Haixu Li ,  Zhanfeng Cao ,  Ke Wang

IPC: H01L27/12 ,  H01L25/075

Abstract: A micro LED display panel and a method for fabricating the same are disclosed, and the micro LED display panel includes a TFT back panel, and a micro LED fixed on the TFT back panel, wherein the TFT back panel includes a substrate, and a first insulation layer and a second insulation layer stacked over the substrate in that order, wherein the first insulation layer includes a groove filled with the second insulation layer, and a normal projection of the groove onto the substrate does not overlap with a normal projection of a TFT area in the TFT back panel onto the substrate, wherein the rigidity of the second insulation layer is lower than the rigidity of the first insulation layer.

公开(公告)号：US20210359063A1

公开(公告)日：2021-11-18

申请号：US16330719

申请日：2018-09-11

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xinhong Lu ,  Ke Wang ,  Hehe Hu ,  Ce Ning ,  Wei Yang

IPC: H01L27/32 ,  H01L29/786

Abstract: An array substrate includes a base substrate; a first thin film transistor on the base substrate and including a first active layer, a first gate electrode, a first source electrode and a first drain electrode; a second thin film transistor on the base substrate and including a second active layer, a second gate electrode, a second source electrode and a second drain electrode; a first gate insulating layer between the first active layer and the first gate electrode; and a second gate insulating layer between the second active layer and the second gate electrode, the second gate insulating layer being different from the first gate insulating layer. The first source electrode, the first drain electrode, and the second gate electrode are in a same layer. The first source electrode and the first drain electrode are on a side of the second gate insulating layer distal to the base substrate.

公开(公告)号：US20210064104A1

公开(公告)日：2021-03-04

申请号：US16643919

申请日：2019-08-14

Applicant: BOE Technology Group Co., Ltd.

Inventor： Haixu Li ,  Zhanfeng Cao ,  Ke Wang ,  Jianguo Wang

IPC: G06F1/18

Abstract: The present disclosure provides a wiring structure, a preparation method thereof, and a display device. The wiring structure includes a substrate; a pre-arranged layer located on the substrate; and an electrode wiring covering the pre-arranged layer; wherein in the direction perpendicular to an extending direction of the electrode wiring and parallel to a plane on which the substrate is located, an orthographic projection of the pre-arranged layer on the substrate is located within an orthographic projection of the electrode wiring on the substrate, and a side surface of the pre-arranged layer is inclined relative to the plane on which the substrate is located.

公开(公告)号：US09502577B2

公开(公告)日：2016-11-22

申请号：US14416227

申请日：2014-04-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ke Wang ,  Seongyeol Yoo ,  Ce Ning ,  Wei Yang

IPC: H01L29/786 ,  H01L21/4763 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L21/47635 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66969 ,  H01L29/78606

Abstract: Provided are oxide thin-film transistor and display device employing the same, and method for manufacturing an oxide thin-film transistor array substrate. A source electrode and a drain electrode are located below an oxide active layer pattern, and a gate electrode is located below the source electrode and the drain electrode, and the gate insulating layer is located between the gate electrode and the source electrode/the drain electrode.

Abstract translation: 提供了氧化物薄膜晶体管和采用该氧化物薄膜晶体管的显示装置，以及制造氧化物薄膜晶体管阵列基板的方法。 源电极和漏极位于氧化物有源层图案的下方，栅电极位于源极和漏电极的下方，栅极绝缘层位于栅电极和源电极/漏电极之间 。

公开(公告)号：US20160284741A1

公开(公告)日：2016-09-29

申请号：US14778257

申请日：2015-04-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ke Wang ,  Seongyeol Yoo

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1368 ,  H01L29/786 ,  G02F1/1343

CPC classification number: H01L27/1288 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136295 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/127 ,  H01L29/66969 ,  H01L29/7869

Abstract: The present invention provides an array substrate fabricating method. The array substrate fabricating method comprises the steps of: forming a semiconductor material layer and a first photoresist layer on a substrate successively, forming a pattern of an active layer comprising thin film transistors by using the semiconductor material layer and the first photoresist layer through photoetching technology, and reserving the first photoresist layer at least on conductive areas of the active layer when the thin film transistors are turned on; and forming a first material layer on the substrate on which the active layer is formed and the first photoresist layer is reserved on the active layer, and forming a pattern comprising first structures by using the first material layer through the photoetching technology. The method is adapted for fabricating an array substrate using metal oxide thin film transistors.

Abstract translation: 本发明提供一种阵列基板的制造方法。 阵列基板制造方法包括以下步骤：连续地在基板上形成半导体材料层和第一光致抗蚀剂层，通过使用半导体材料层和第一光致抗蚀剂层通过光刻技术形成包括薄膜晶体管的有源层的图案 并且当所述薄膜晶体管导通时，至少在所述有源层的导电区域上保留所述第一光致抗蚀剂层; 以及在其上形成有源层的衬底上形成第一材料层，并且在有源层上保留第一光致抗蚀剂层，以及通过使用第一材料层通过光刻技术形成包括第一结构的图案。 该方法适用于使用金属氧化物薄膜晶体管制造阵列基板。

公开(公告)号：US12294043B2

公开(公告)日：2025-05-06

申请号：US17280387

申请日：2020-01-22

Applicant: BOE Technology Group Co., Ltd.

Inventor： Wei Yang ,  Ke Wang ,  Muxin Di

IPC: H01L33/62 ,  H01L33/00

Abstract: The present application discloses a drive backplane and a preparation method thereof, a display panel, and a display device. The drive backplane includes a flexible substrate provided with a first via hole; a first passivation layer located on a side of the flexible substrate and provided with a second via hole, an orthographic projection of the second via hole being at least partially overlapped with an orthographic projection of the first via hole; a thin film transistor located on a side, facing away from the flexible substrate, of the first passivation layer; and an electrical connecting structure, including a signal trace and a connecting terminal.

公开(公告)号：US12279467B2

公开(公告)日：2025-04-15

申请号：US17769022

申请日：2021-06-11

Applicant: BOE Technology Group Co., Ltd.

Inventor： Ke Wang ,  Zhanfeng Cao ,  Qi Qi ,  Yan Qu

IPC: H10H20/857 ,  H01L25/16

Abstract: A substrate, a backlight module, and a display apparatus, which relates to the technical field of display. The substrate is configured to display or provide a backlight, and the substrate includes: a bonding region (OB) and a plurality of light-emitting regions (OA); each of the plurality of light-emitting regions (OA) includes a first metal layer (1) and a first conductive adhesive (2) located on the first metal layer (1), the first conductive adhesive (2) is a photo-curing conductive adhesive; and the bonding region (OB) includes a second metal layer (3) and a second conductive adhesive (4) located on the second metal layer (3).

公开(公告)号：US12278213B2

公开(公告)日：2025-04-15

申请号：US17422220

申请日：2020-10-21

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Mingxing Wang ,  Meng Yan ,  Qingxun Zhang ,  Qian Wu ,  Xuan Feng ,  Xiawei Yun ,  Guangcai Yuan ,  Xue Dong ,  Muxin Di ,  Zhiwei Liang ,  Ke Wang

IPC: H01L27/15 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H10K59/35

Abstract: A display substrate and a display device are provided. The display substrate includes a backplane including a plurality of pixel regions; and light emitting units arranged in one-to-one correspondence with the plurality of pixel regions. Each light emitting unit includes light emitting sub-units arranged in a plurality of rows and a plurality of columns, each row of light emitting sub-units includes a plurality of light emitting sub-units arranged along a row direction, each column of light emitting sub-units includes one light emitting sub-unit, and orthographic projections of light emitting regions of two adjacent columns of light emitting sub-units on a first straight line extending along a column direction are not overlapped; and in each light emitting unit, there is no gap between orthographic projections of the light emitting regions of the two adjacent columns of light emitting sub-units on a second straight line extending along the row direction.