公开(公告)号：US20070026668A1

公开(公告)日：2007-02-01

申请号：US11457888

申请日：2006-07-17

申请人： Hun-Jan Tao ,  Ryan Chen ,  Mong-Song Liang

发明人： Hun-Jan Tao ,  Ryan Chen ,  Mong-Song Liang

IPC分类号： H01L21/465

CPC分类号： H01L21/31116 ,  H01L21/76802 ,  H01L21/76807

摘要： A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer is disclosed, with the method using a high density, high radical concentration plasma containing fluorine and oxygen to minimize back sputtering of copper underlying the bottom etch stop layer and surface roughening of the low-k interlayer dielectric caused by the plasma.

摘要翻译： 公开了一种通过蚀刻底部蚀刻停止层去除铜镶嵌结构中的氮化硅或氮化物基底部蚀刻停止层的方法，该方法使用含有氟和氧的高密度，高自由基浓度等离子体来最小化背面 底层蚀刻停止层下面的铜的溅射以及由等离子体引起的低k层间电介质的表面粗糙化。

公开(公告)号：US20060205224A1

公开(公告)日：2006-09-14

申请号：US11318934

申请日：2005-12-27

申请人： Ming-Jie Huang ,  Shu-Chih Yang ,  Huan-Just Lin ,  Yung-Tin Chen ,  Hun-Jan Tao

发明人： Ming-Jie Huang ,  Shu-Chih Yang ,  Huan-Just Lin ,  Yung-Tin Chen ,  Hun-Jan Tao

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/32139 ,  H01L21/28123

摘要： Large-scale trimming for forming ultra-narrow gates for semiconductor devices is disclosed. A hard mask layer on a semiconductor wafer below a patterned soft mask layer on the semiconductor wafer is etched to narrow a width of the hard mask layer. The hard mask layer is trimmed to further narrow the width of the hard mask layer, where the soft mask layer has been removed. At least a gate electrode layer below the hard mask layer on the semiconductor wafer is etched, resulting in the gate electrode layer having a width substantially identical to the width of the hard mask layer as trimmed. The gate electrode layer as etched forms the ultra-narrow gate electrode on the semiconductor wafer, where the hard mask layer has been removed.

公开(公告)号：US07078351B2

公开(公告)日：2006-07-18

申请号：US10361875

申请日：2003-02-10

申请人： Yuan-Hung Chiu ,  Ming-Huan Tsai ,  Hun-Jan Tao ,  Jeng-Horng Chen

发明人： Yuan-Hung Chiu ,  Ming-Huan Tsai ,  Hun-Jan Tao ,  Jeng-Horng Chen

IPC分类号： H01L21/302

CPC分类号： H01L21/0276 ,  H01L21/0332 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/76802

摘要： A layer of Anti Reflective Coating (ARC) is first deposited over the surface of a silicon based or oxide based semiconductor surface, a dual hardmask is deposited over the surface of the layer of ARC. A layer of soft mask material is next coated over the surface of the dual hardmask layer, the layer of soft mask material is exposed, creating a soft mask material mask. The upper layer of the dual hardmask layer is next patterned in accordance with the soft mask material mask, the soft mask material mask is removed from the surface. The lower layer of the hardmask layer is then patterned after which the layer of ARC is patterned, both layers are patterned in accordance with the patterned upper layer of the dual hardmask layer. The substrate is now patterned in accordance with the patterned upper and lower layer of the dual hardmask layer and the patterned layer of ARC. The patterned upper and lower layers of the hardmask layer and the patterned layer of ARC are removed from the surface of the silicon based or oxide based semiconductor surface.

摘要翻译： 首先将抗反射涂层（ARC）沉积在硅基或氧化物基半导体表面的表面上，双重硬掩模沉积在ARC层的表面上。 然后将一层软掩模材料涂覆在双重硬掩模层的表面上，该软掩模材料层被暴露，形成柔软的掩模材料掩模。 根据软掩模材料掩模，双硬掩模层的上层接下来图案化，从表面去除软掩模材料掩模。 然后对硬掩模层的下层进行图案化，之后对ARC层进行构图，根据双重硬掩模层的图案化上层对两层进行图案化。 衬底现在根据双重硬掩模层的图案化的上下层和ARC的图案化层进行图案化。 从硅基或氧化物基半导体表面的表面去除硬掩模层的图案化的上层和下层以及ARC的图案化层。

公开(公告)号：US07074727B2

公开(公告)日：2006-07-11

申请号：US10615628

申请日：2003-07-09

申请人： Peng-Fu Hsu ,  Jyu-Horng Shieh ,  Yung-Cheng Lu ,  Hun-Jan Tao ,  Yuan-Hung Chiu

发明人： Peng-Fu Hsu ,  Jyu-Horng Shieh ,  Yung-Cheng Lu ,  Hun-Jan Tao ,  Yuan-Hung Chiu

IPC分类号： C08G77/00 ,  H01L21/768

CPC分类号： C08G77/38

摘要： Low-k organosilicate dielectric material can be exposed to a series of reagents, including a halogenation reagent, an alkylation reagent, and a termination reagent, in order to reverse degradation of dielectric properties caused by previous processing steps.

摘要翻译： 低k有机硅酸盐电介质材料可以暴露于一系列试剂，包括卤化试剂，烷基化试剂和终止试剂，以反转由以前的处理步骤引起的介电性质的退化。

公开(公告)号：US20060086690A1

公开(公告)日：2006-04-27

申请号：US10971265

申请日：2004-10-21

申请人： Ming-Huan Tsai ,  Fong-Yuh Yen ,  Hun-Jan Tao

发明人： Ming-Huan Tsai ,  Fong-Yuh Yen ,  Hun-Jan Tao

IPC分类号： C23F1/00 ,  C03C25/68 ,  B44C1/22

CPC分类号： H01L21/31116

摘要： A method of dry etching a dielectric layer is provided that prevents or significantly reduces deep ultraviolet photoresist damage and bird's beak problems. The dry etch method provided comprises the steps of providing a substrate having a dielectric layer overlying at least a portion of the substrate's surface; applying a deep ultraviolet (DUV) photoresist mask having a pattern of exposed area on at least a portion of the dielectric layer; and etching the masked dielectric layer with a plasma formed from a mixture of gases comprising a gaseous fluorine species, hydrogen, and helium.

摘要翻译： 提供了干蚀刻电介质层的方法，其防止或显着降低深紫外光致抗蚀剂损伤和鸟嘴问题。 所提供的干蚀刻方法包括以下步骤：提供具有覆盖在基底表面的至少一部分上的介电层的基底; 在所述电介质层的至少一部分上施加具有暴露区域图案的深紫外（DUV）光致抗蚀剂掩模; 并用由包含气态氟物质，氢气和氦气的气体混合物形成的等离子体蚀刻掩蔽的电介质层。

公开(公告)号：US06974730B2

公开(公告)日：2005-12-13

申请号：US10739476

申请日：2003-12-17

申请人： Carlos H. Diaz ,  Yi-Ming Sheu ,  Syun-Ming Jang ,  Hun-Jan Tao ,  Fu-Liang Yang

发明人： Carlos H. Diaz ,  Yi-Ming Sheu ,  Syun-Ming Jang ,  Hun-Jan Tao ,  Fu-Liang Yang

IPC分类号： H01L21/336 ,  H01L29/786

CPC分类号： H01L29/66772 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78621 ,  H01L29/78654

摘要： A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of source/drain regions prior to forming a pair of lightly doped extension regions within the field effect transistor device. In accord with the foregoing features, the field effect transistor device is fabricated with enhanced performance.

摘要翻译： 用于形成场效应晶体管器件的方法采用半导体衬底的自对准蚀刻以与一对凸起的源极/漏极区域结合形成凹陷沟道区域。 该方法还提供了在场效应晶体管器件内形成一对轻掺杂的延伸区域之前，对成对的源/漏区进行形成和热退火。 根据上述特征，以增强的性能制造场效应晶体管器件。

公开(公告)号：US20050133827A1

公开(公告)日：2005-06-23

申请号：US10738239

申请日：2003-12-17

申请人： Ming-Jie Huang ,  Shu-Chih Yang ,  Huan-Just Lin ,  Yung-Tin Chen ,  Hun-Jan Tao

发明人： Ming-Jie Huang ,  Shu-Chih Yang ,  Huan-Just Lin ,  Yung-Tin Chen ,  Hun-Jan Tao

IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L29/745

CPC分类号： H01L21/32139 ,  H01L21/28123

摘要： Large-scale trimming for forming ultra-narrow gates for semiconductor devices is disclosed. A hard mask layer on a semiconductor wafer below a patterned soft mask layer on the semiconductor wafer is etched to narrow a width of the hard mask layer. The hard mask layer is trimmed to further narrow the width of the hard mask layer, where the soft mask layer has been removed. At least a gate electrode layer below the hard mask layer on the semiconductor wafer is etched, resulting in the gate electrode layer having a width substantially identical to the width of the hard mask layer as trimmed. The gate electrode layer as etched forms the ultra-narrow gate electrode on the semiconductor wafer, where the hard mask layer has been removed.

摘要翻译： 公开了用于形成用于半导体器件的超窄栅极的大规模修整。 蚀刻在半导体晶片上的图案化软掩模层下方的半导体晶片上的硬掩模层，以使硬掩模层的宽度变窄。 修剪硬掩模层以进一步缩小已经去除软掩模层的硬掩模层的宽度。 蚀刻半导体晶片上的硬掩模层下方的至少栅极电极层，导致栅极电极层的宽度与被修整的硬掩模层的宽度基本相同。 蚀刻的栅极电极层形成半导体晶片上的超窄栅电极，其中硬掩模层被去除。

公开(公告)号：US20050095869A1

公开(公告)日：2005-05-05

申请号：US10701825

申请日：2003-11-05

申请人： Hun-Jan Tao ,  Ryan Chen ,  Mong-Song Liang

发明人： Hun-Jan Tao ,  Ryan Chen ,  Mong-Song Liang

IPC分类号： H01L21/302 ,  H01L21/311 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/31116 ,  H01L21/76802 ,  H01L21/76807

摘要： A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer using a high density, high radical concentration plasma containing fluorine and oxygen to minimize back sputtering of copper underlying the bottom etch stop layer and surface roughening of the low-k interlayer dielectric caused by the plasma.

摘要翻译： 通过使用包含氟和氧的高密度，高自由基浓度的等离子体蚀刻底部蚀刻停止层来去除铜镶嵌结构中的氮化硅或氮化物基底部蚀刻停止层的方法，以最小化底部的铜的反溅射 蚀刻停止层和由等离子体引起的低k层间电介质的表面粗糙化。

公开(公告)号：US06869868B2

公开(公告)日：2005-03-22

申请号：US10318459

申请日：2002-12-13

申请人： Hsien-Kuang Chiu ,  Fang-Cheng Chen ,  Haur-Ywh Chen ,  Hun-Jan Tao ,  Yuan-Hung Chiu

发明人： Hsien-Kuang Chiu ,  Fang-Cheng Chen ,  Haur-Ywh Chen ,  Hun-Jan Tao ,  Yuan-Hung Chiu

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/4763

CPC分类号： H01L29/785 ,  H01L21/28088 ,  H01L29/42384 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66795

摘要： A method of forming a composite gate structure for a planar MOSFET device, as well as for vertical, double gate, FINFET device, has been developed. The method features a composite gate structure comprised of an overlying silicon gate structure shape, and an underlying titanium nitride gate structure shape. The titanium nitride component allows a lower work function, and thus lower device operating voltages to be realized when compared to counterpart gate structures formed with only polysilicon. A novel, two step gate structure definition procedure, featuring an anisotropic first etch procedure for definition of the polysilicon gate structure shape, followed by a wet or dry isotopic second etch procedure for definition of the titanium nitride gate structure shape, is employed.

摘要翻译： 已经开发了形成用于平面MOSFET器件的复合栅极结构以及用于垂直双栅极FINFET器件的方法。 该方法具有由上覆硅栅极结构形状和下面的氮化钛栅极结构形状组成的复合栅极结构。 与仅由多晶硅形成的对应栅极结构相比，氮化钛部件允许较低的功函数，因此降低器件工作电压。 采用新颖的两步栅极结构定义方法，其特征在于用于定义多晶硅栅极结构形状的各向异性第一蚀刻工艺，随后是用于定义氮化钛栅极结构形状的湿式或干式同位素第二蚀刻工艺。

公开(公告)号：US06780782B1

公开(公告)日：2004-08-24

申请号：US10357579

申请日：2003-02-04

申请人： Ming-Huan Tsai ,  Hun-Jan Tao ,  Tsang Jiuh Wu ,  Ju Wang Hsu

发明人： Ming-Huan Tsai ,  Hun-Jan Tao ,  Tsang Jiuh Wu ,  Ju Wang Hsu

IPC分类号： H01L21302

CPC分类号： H01L21/76802 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144

摘要： An improved method of etching very small contact holes through dielectric layers used to separate conducting layers in multilevel integrated circuits formed on semiconductor substrates has been developed. The method uses bi-level ARC coatings in the resist structure and a unique combination of gaseous components in a plasma etching process which is used to dry develop the bi-level resist mask as well as etch through a silicon oxide dielectric layer. The gaseous components comprise a mixture of a fluorine containing gas, such as C4F8, C5F8, C4F6, CHF3 or similar species, an inert gas, such as helium or argon, an optional weak oxidant, such as CO or O2 or similar species, and a nitrogen source, such as N2, N2O, or NH3 or similar species. The patterned masking layer can be used to reliably etch contact holes in silicon oxide layers on semiconductor substrates, where the holes have diameters of about 0.1 micron or less.

摘要翻译： 已经开发了一种通过介电层蚀刻非常小的接触孔的改进方法，其用于在半导体衬底上形成的多层集成电路中分离导电层。 该方法在抗蚀剂结构中使用双层ARC涂层，并且在等离子体蚀刻工艺中使用气态组分的独特组合，其用于干燥显影双电平抗蚀剂掩模以及通过氧化硅介电层进行蚀刻。 气态组分包括含氟气体如C 4 F 8，C 5 F 8，C 4 F 6，CHF 3或类似物质，惰性气体如氦气或氩气，任选的弱氧化剂如CO或O 2或类似物质的混合物，以及 氮源，例如N 2，N 2 O或NH 3或类似物质。 图案化掩模层可用于可靠地蚀刻半导体衬底上的氧化硅层中的接触孔，其中孔的直径为约0.1微米或更小。