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79 条记录 (耗时 0.027 秒)

    Configurable decoder for addressing a memory
    62.
    发明授权
    Configurable decoder for addressing a memory 有权
    用于寻址存储器的可配置解码器

    公开(公告)号：US06747903B1

    公开(公告)日：2004-06-08

    申请号：US10046939

    申请日：2002-01-14

    申请人： Philip Y. Pan ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Gopinath Rangan ,  In Whan Kim ,  Yan Chong ,  Tzung-Chin Chang

    发明人： Philip Y. Pan ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Gopinath Rangan ,  In Whan Kim ,  Yan Chong ,  Tzung-Chin Chang

    IPC分类号： G11C700

    CPC分类号： H03K19/1776 ,  G11C8/16

    摘要： Methods and apparatus for decoding addresses in a memory to provide mixed input and output data widths. A method includes receiving an address portion comprising a first number of bits. A second number of bits of the address portion are blocked, where the second number is less than the first number. A third number of bits are not blocked, and the third number plus the second number equal the first number. The third number of bits are decoded and a fourth number of memory cells are selected. The fourth number is equal to two to the power of the second number. A fourth number of data bits are received and multiplexed to the selected memory cells. The data bits are written to the selected memory cells.

    摘要翻译： 用于解码存储器中的地址以提供混合的输入和输出数据宽度的方法和装置。 一种方法包括接收包括第一位数的地址部分。 地址部分的第二位数被阻塞，其中第二个数字小于第一个数字。 第三个位数不被阻塞，第三个数字加上第二个数字等于第一个数字。 第三位数被解码，并且选择第四数量的存储单元。 第四个数字等于第二个数字的两倍。 接收第四数量的数据位并将其多路复用到选择的存储单元。 数据位被写入选定的存储单元。

    Programming mode selection with JTAG circuits
    63.
    发明授权
    Programming mode selection with JTAG circuits 有权
    使用JTAG电路进行编程模式选择

    公开(公告)号：US06681378B2

    公开(公告)日：2004-01-20

    申请号：US10175980

    申请日：2002-06-19

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Richard G. Cliff

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Richard G. Cliff

    IPC分类号： G06F1750

    CPC分类号： H03K19/1732 ,  G01R31/318555 ,  G06F11/2273 ,  H03K19/17744 ,  H03K19/17748

    摘要： A technique to provide higher system performance by increasing amount of data that may be transferred in parallel is to increase the number of external pins available for the input and output of user data (user I/O). Specifically, a technique is to reduce the number of dedicated pins used for user I/O, leaving more external pins available for user I/O. The dedicated pins used to implement a function such as the JTAG boundary scan architecture may be also be used to provide other functionality, such as to select the programming modes. In a specific embodiment, a JTAG instruction code that is not already used for a JTAG boundary scan instruction stored in an instruction register (220) may be used to replace the programming mode select pins (252) in a programmable logic device (PLD).

    摘要翻译： 通过增加并行传输的数据量来提供更高系统性能的技术是增加可用于输入和输出用户数据（用户I / O）的外部引脚数。 具体来说，一种技术是减少用于用户I / O的专用引脚数，从而为用户I / O提供更多的外部引脚。 用于实现诸如JTAG边界扫描架构的功能的专用引脚也可用于提供其他功能，例如选择编程模式。 在具体实施例中，也可以使用尚未用于存储在指令寄存器（220）中的JTAG边界扫描指令的JTAG指令代码来替代可编程逻辑器件（PLD）中的编程模式选择引脚（252）。

    Programming mode selection with JTAG circuits
    64.
    发明授权
    Programming mode selection with JTAG circuits 失效
    使用JTAG电路进行编程模式选择

    公开(公告)号：US06421812B1

    公开(公告)日：2002-07-16

    申请号：US09094186

    申请日：1998-06-09

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Richard G. Cliff

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Richard G. Cliff

    IPC分类号： G06F1750

    CPC分类号： H03K19/1732 ,  G01R31/318555 ,  G06F11/2273 ,  H03K19/17744 ,  H03K19/17748

    摘要： A technique to provide higher system performance by increasing amount of data that may be transferred in parallel is to increase the number of external pins available for the input and output of user data (user I/O). Specifically, a technique is to reduce the number of dedicated pins used for user I/O, leaving more external pins available for user I/O. The dedicated pins used to implement a function such as the JTAG boundary scan architecture may be also be used to provide other functionality, such as to select the programming modes. In a specific embodiment, a JTAG instruction code that is not already used for a JTAG boundary scan instruction stored in an instruction register (220) may be used to replace the programming mode select pins (252) in a programmable logic device (PLD).

    摘要翻译： 通过增加并行传输的数据量来提供更高系统性能的技术是增加可用于输入和输出用户数据（用户I / O）的外部引脚数。 具体来说，一种技术是减少用于用户I / O的专用引脚数，从而为用户I / O提供更多的外部引脚。 用于实现诸如JTAG边界扫描架构的功能的专用引脚也可用于提供其他功能，例如选择编程模式。 在具体实施例中，也可以使用尚未用于存储在指令寄存器（220）中的JTAG边界扫描指令的JTAG指令代码来替代可编程逻辑器件（PLD）中的编程模式选择引脚（252）。

    Configurable input-output (I/O) circuitry with pre-emphasis circuitry
    65.
    发明授权
    Configurable input-output (I/O) circuitry with pre-emphasis circuitry 有权
    具有预加重电路的可组态输入输出（I / O）电路

    公开(公告)号：US08390315B1

    公开(公告)日：2013-03-05

    申请号：US13354780

    申请日：2012-01-20

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen

    IPC分类号： H03K19/013 ,  H03K17/16

    CPC分类号： H03K19/01721 ,  H03K19/018571

    摘要： Circuits and techniques for operating an integrated circuit (IC) with a configurable input-output circuit are disclosed. A disclosed circuit includes a single-ended input-output buffer coupled to an output terminal. The single-ended input-output buffer is operable to transmit an input signal to the output terminal as an output signal. A pre-emphasis circuit that is operable to sharpen a first edge and a second edge of the output signal is coupled between the single-ended input-output buffer and the output terminal. The first edge of the output signal is sharpened when the input signal switches from a first logic level to a second logic level while the second edge of the output signal is sharpened when the input signal switches from the second logic level to the first logic level.

    摘要翻译： 公开了具有可配置的输入 - 输出电路来操作集成电路（IC）的电路和技术。 所公开的电路包括耦合到输出端子的单端输入 - 输出缓冲器。 单端输入 - 输出缓冲器可用于将输入信号作为输出信号发送到输出端。 用于锐化输出信号的第一边缘和第二边缘的预加重电路耦合在单端输入 - 输出缓冲器和输出端子之间。 当输入信号从第一逻辑电平切换到第二逻辑电平时，输出信号的第一边缘被锐化，而当输入信号从第二逻辑电平切换到第一逻辑电平时，输出信号的第二边沿被锐化。

    Level shifter circuits and methods
    66.
    发明授权
    Level shifter circuits and methods 有权
    电平移位电路和方法

    公开(公告)号：US07994821B1

    公开(公告)日：2011-08-09

    申请号：US12753389

    申请日：2010-04-02

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen

    IPC分类号： H03K19/0175

    CPC分类号： H03K3/356069

    摘要： A level shifter circuit includes first and second transistors coupled in series and third and fourth transistors coupled in series. The fourth transistor is coupled to a first node between the first and the second transistors. The level shifter circuit also includes fifth and sixth transistors coupled in series and seventh and eighth transistors coupled in series. The eighth transistor is coupled to a second node between the fifth and the sixth transistors. The second and the eighth transistors receive a first input signal at control inputs. The fourth and the sixth transistors receive a second input signal at control inputs. The second input signal is inverted relative to the first input signal.

    摘要翻译： 电平移位器电路包括串联耦合的第一和第二晶体管，以及串联耦合的第三和第四晶体管。 第四晶体管耦合到第一和第二晶体管之间的第一节点。 电平移位器电路还包括串联耦合的第五和第六晶体管，以及串联耦合的第七和第八晶体管。 第八晶体管耦合到第五和第六晶体管之间的第二节点。 第二和第八晶体管在控制输入端接收第一输入信号。 第四和第六晶体管在控制输入端接收第二输入信号。 第二输入信号相对于第一输入信号反相。

    Technique to test an integrated circuit using fewer pins
    68.
    发明授权
    Technique to test an integrated circuit using fewer pins 失效
    使用较少引脚测试集成电路的技术

    公开(公告)号：US06691267B1

    公开(公告)日：2004-02-10

    申请号：US09094221

    申请日：1998-06-09

    申请人： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Xiaobao Wang

    发明人： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Xiaobao Wang

    IPC分类号： G01R3128

    CPC分类号： H03K19/17764 ,  G01R31/318516 ,  G01R31/318555 ,  G06F11/2273 ,  H03K19/17744

    摘要： A technique to implement functions requiring fewer pins of an integrated circuit to serially transfer data into the integrated circuit for multiple logic blocks. By reducing the required pins, this permits downbonding of the integrated circuit into a package with fewer pins. This technique may be used to implement test functions in a programmable logic device. Test data may be serially input using a test pin (310) for two or more columns (320) of logic blocks. The test data is stored in an A register (330), and may be later transferred into a B register (335).

    摘要翻译： 实现需要较少的集成电路引脚的功能以将数据串行传输到用于多个逻辑块的集成电路的技术。 通过减少所需的引脚，可以将集成电路下降到具有较少引脚的封装中。 该技术可用于在可编程逻辑器件中实现测试功能。 测试数据可以使用针对逻辑块的两列或多列（320）的测试引脚（310）进行串行输入。 测试数据存储在A寄存器（330）中，并且可以稍后传送到B寄存器（335）。

    Programmable I/O element circuit for high speed logic devices
    69.
    发明授权
    Programmable I/O element circuit for high speed logic devices 有权
    用于高速逻辑器件的可编程I / O元件电路

    公开(公告)号：US06686769B1

    公开(公告)日：2004-02-03

    申请号：US10017666

    申请日：2001-12-14

    申请人： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Phillip Pan ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Xiaobao Wang ,  Tzung-Chin Chang

    发明人： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Phillip Pan ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Xiaobao Wang ,  Tzung-Chin Chang

    IPC分类号： H03K19173

    CPC分类号： C07K16/28 ,  A61K2039/505 ,  C07K14/47

    摘要： A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed I/O modes such as double data rate and zero bus turnaround. The I/O element may include an input block with two registers for registering input signals from the terminal upon alternate clock edges. In addition or alternatively, it may include an output block with two registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those signals. For bidirectional terminals, the multiplexer output is connectable to the I/O terminal via an output buffer, and an output enable block provides an enable signal to a gating input of the output buffer. Programmable delays may be included in the input, output, and output enable paths, in particular to provide a slower turn-on time than turn-off time for the output buffer.

    摘要翻译： 用于逻辑阵列的I / O端子的可编程I / O元件适用于根据高速I / O模式（如双数据速率和零总线周转）进行工作。 I / O元件可以包括具有两个寄存器的输入块，用于在备用时钟边缘上从终端注册输入信号。 另外或替代地，它可以包括具有两个寄存器的输出块，该两个寄存器在相同的时钟沿上单独地寄存来自阵列的输出信号，以及交替地输出这些信号的多路复用器。 对于双向端子，多路复用器输出可通过输出缓冲器连接到I / O端子，并且输出使能块向输出缓冲器的选通输入提供使能信号。 可编程延迟可以包括在输入，输出和输出使能路径中，特别是提供比输出缓冲器的关断时间更慢的导通时间。