公开(公告)号：US20090239334A1

公开(公告)日：2009-09-24

申请号：US12052581

申请日：2008-03-20

申请人： Matthew J. Breitwisch ,  Matthew Colburn ,  Eric Joseph ,  Chung Hon Lam ,  Deborah A. Neumayer ,  Alejandro G. Schrott

发明人： Matthew J. Breitwisch ,  Matthew Colburn ,  Eric Joseph ,  Chung Hon Lam ,  Deborah A. Neumayer ,  Alejandro G. Schrott

IPC分类号： H01L21/00

CPC分类号： H01L45/1683 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

摘要： A method of manufacturing a memory device is provided that in one embodiment includes providing an interlevel dielectric layer including a first via containing a memory material; forming at least one insulating layer on an upper surface of the memory material and the interlevel dielectric layer; forming an cavity through a portion of a thickness of the at least one insulating layer; forming a copolymer mask in at least the cavity, the copolymer mask including at least one opening that provides an exposed surface of a remaining portion of the at least one insulating layer that overlies the memory material; etching the exposed surface of the remaining portion of the at least one insulating layer to provide a second via to the memory material; and forming a conductive material within the second via in electrical contact with the memory material.

摘要翻译： 提供了一种制造存储器件的方法，其在一个实施例中包括提供包括含有存储材料的第一通孔的层间介电层; 在所述存储材料和所述层间电介质层的上表面上形成至少一个绝缘层; 通过所述至少一个绝缘层的厚度的一部分形成空腔; 在至少所述空腔中形成共聚物掩模，所述共聚物掩模包括至少一个开口，所述至少一个开口提供覆盖所述存储材料的所述至少一个绝缘层的剩余部分的暴露表面; 蚀刻所述至少一个绝缘层的剩余部分的暴露表面以向所述存储材料提供第二通孔; 以及在所述第二通孔内与所述记忆材料电接触形成导电材料。

公开(公告)号：US20120276688A1

公开(公告)日：2012-11-01

申请号：US13546684

申请日：2012-07-11

申请人： Matthew J. Breitwisch ,  Chieh-Fang Chen ,  Shih-Hung Chen ,  Eric A. Joseph ,  Chung Hon Lam ,  Michael F. Lofaro ,  Hsiang-Lan Lung ,  Alejandro G. Schrott ,  Min Yang

发明人： Matthew J. Breitwisch ,  Chieh-Fang Chen ,  Shih-Hung Chen ,  Eric A. Joseph ,  Chung Hon Lam ,  Michael F. Lofaro ,  Hsiang-Lan Lung ,  Alejandro G. Schrott ,  Min Yang

IPC分类号： H01L21/06

CPC分类号： H01L45/06 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1683

摘要： A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.

摘要翻译： 一种形成与相变材料对准的位线的方法，包括在下电极的一部分上形成牺牲材料的基座并且形成与所述牺牲材料相邻的至少一个电介质材料，其中所述至少一种电介质材料具有 上表面与牺牲材料的基座的上表面基本共面。 牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。 在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。 还提供了自对准的回蚀工艺。

公开(公告)号：US20110037042A1

公开(公告)日：2011-02-17

申请号：US12541595

申请日：2009-08-14

申请人： Matthew J. Breitwisch ,  Eric A. Joseph ,  Alejandro G. Schrott ,  Xiaoyan Shao

发明人： Matthew J. Breitwisch ,  Eric A. Joseph ,  Alejandro G. Schrott ,  Xiaoyan Shao

IPC分类号： H01L47/00 ,  H01L21/16

CPC分类号： H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1608 ,  H01L45/1683 ,  H01L45/1691

摘要： A method for fabricating a phase change memory device including memory cells includes patterning a via to a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, lining each via with a conformal conductive seed layer to the contact surface, forming a dielectric layer covering the conductive seed layer, and etching a center region of each via to the contact surface to expose the conformal conductive seed layer at the contact surface. The method further includes electroplating phase change material on exposed portions of the conformal conductive seed layer, recessing the phase change material within the center region forming a conductive material that remains conductive upon oxidation, on the recessed phase change material, oxidizing edges of the conformal conductive seed layer formed along sides of each via, and forming a top electrode over each memory cell.

公开(公告)号：US08023345B2

公开(公告)日：2011-09-20

申请号：US12391693

申请日：2009-02-24

申请人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Stefanie R. Chiras ,  Ibrahim M. Elfadel ,  Michele M. Franceschini ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Thomas Mittelholzer ,  Mayank Sharma

发明人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Stefanie R. Chiras ,  Ibrahim M. Elfadel ,  Michele M. Franceschini ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Thomas Mittelholzer ,  Mayank Sharma

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/02 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C29/021 ,  G11C29/028 ,  G11C2013/0092

摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.

摘要翻译： 提供了用于向内存位置迭代地写入内容的系统，方法和设备。 统计模型用于确定将所需内容写入存储器位置的脉冲序列。 内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。 对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。 读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。 统计模型和查询表可用于选择和修改脉冲。 自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

公开(公告)号：US08115186B2

公开(公告)日：2012-02-14

申请号：US12498840

申请日：2009-07-07

申请人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Eric Andrew Joseph ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Alejandro Gabriel Schrott

发明人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Eric Andrew Joseph ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Alejandro Gabriel Schrott

IPC分类号： H01L29/02 ,  H01L47/00

CPC分类号： H01L45/144 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1666

摘要： A memory cell is fabricated by forming a dielectric layer and patterning a hole in the dielectric layer. Patterning the hole is accomplished at least in part by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material. A phase change feature is then formed in contact with the dielectric layer such that a portion of the phase change feature at least partially fills the hole in the dielectric layer. At least a portion of the patterned dielectric layer remains in the ultimate memory cell.

摘要翻译： 通过形成电介质层并在电介质层中构图孔来制造存储单元。 至少部分地通过在有效去除与催化材料接触的电介质层的那些区域的条件下在反应物存在下使介电层与催化材料接触来对孔进行图案化。 然后形成与电介质层接触的相变特征，使得相变特征的一部分至少部分地填充介电层中的孔。 图案化介电层的至少一部分保留在最终存储单元中。

公开(公告)号：US20080265234A1

公开(公告)日：2008-10-30

申请号：US11741781

申请日：2007-04-30

申请人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Eric Andrew Joseph ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Alejandro Gabriel Schrott

发明人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Eric Andrew Joseph ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Alejandro Gabriel Schrott

IPC分类号： H01L45/00

CPC分类号： H01L45/144 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1666

摘要： A memory cell is fabricated by forming a dielectric layer and patterning a hole in the dielectric layer. Patterning the hole is accomplished at least in part by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material. A phase change feature is then formed in contact with the dielectric layer such that a portion of the phase change feature at least partially fills the hole in the dielectric layer. At least a portion of the patterned dielectric layer remains in the ultimate memory cell.

摘要翻译： 通过形成电介质层并在电介质层中构图孔来制造存储单元。 至少部分地通过在有效去除与催化材料接触的电介质层的那些区域的条件下在反应物存在下使介电层与催化材料接触来对孔进行图案化。 然后形成与电介质层接触的相变特征，使得相变特征的一部分至少部分地填充介电层中的孔。 图案化介电层的至少一部分保留在最终存储单元中。

公开(公告)号：US08897062B2

公开(公告)日：2014-11-25

申请号：US13150690

申请日：2011-06-01

申请人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Stefanie R. Chiras ,  Ibrahim M. Elfadel ,  Michele M. Franceschini ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Thomas Mittelholzer ,  Mayank Sharma

发明人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Stefanie R. Chiras ,  Ibrahim M. Elfadel ,  Michele M. Franceschini ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Thomas Mittelholzer ,  Mayank Sharma

IPC分类号： G11C11/00 ,  G11C13/00 ,  G11C29/02

CPC分类号： G11C29/02 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C29/021 ,  G11C29/028 ,  G11C2013/0092

摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.

摘要翻译： 提供了用于向内存位置迭代地写入内容的系统，方法和设备。 统计模型用于确定将所需内容写入存储器位置的脉冲序列。 内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。 对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。 读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。 统计模型和查询表可用于选择和修改脉冲。 自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

公开(公告)号：US20110228600A1

公开(公告)日：2011-09-22

申请号：US13150690

申请日：2011-06-01

申请人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Stefanie R. Chiras ,  Ibrahim M. Elfadel ,  Michele M. Franceschini ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Thomas Mittelholzer ,  Mayank Sharma

发明人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Stefanie R. Chiras ,  Ibrahim M. Elfadel ,  Michele M. Franceschini ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Thomas Mittelholzer ,  Mayank Sharma

IPC分类号： G11C11/21

CPC分类号： G11C29/02 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C29/021 ,  G11C29/028 ,  G11C2013/0092

摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.

摘要翻译： 提供了用于向内存位置迭代地写入内容的系统，方法和设备。 统计模型用于确定将所需内容写入存储器位置的脉冲序列。 内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。 对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。 读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。 统计模型和查询表可用于选择和修改脉冲。 自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

公开(公告)号：US20100214829A1

公开(公告)日：2010-08-26

申请号：US12391693

申请日：2009-02-24

申请人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Stefanie R. Chiras ,  Ibrahim M. Elfadel ,  Michele M. Franceschini ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Thomas Mittelholzer ,  Mayank Sharma

发明人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Stefanie R. Chiras ,  Ibrahim M. Elfadel ,  Michele M. Franceschini ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Thomas Mittelholzer ,  Mayank Sharma

IPC分类号： G11C11/00

CPC分类号： G11C29/02 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C29/021 ,  G11C29/028 ,  G11C2013/0092

摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.

摘要翻译： 提供了用于向内存位置迭代地写入内容的系统，方法和设备。 统计模型用于确定将所需内容写入存储器位置的脉冲序列。 内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。 对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。 读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。 统计模型和查询表可用于选择和修改脉冲。 自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

公开(公告)号：US20090294748A1

公开(公告)日：2009-12-03

申请号：US12498840

申请日：2009-07-07

申请人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Eric Andrew Joseph ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Alejandro Gabriel Schrott

发明人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Eric Andrew Joseph ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Alejandro Gabriel Schrott

IPC分类号： H01L45/00

CPC分类号： H01L45/144 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1666

摘要： A memory cell is fabricated by forming a dielectric layer and patterning a hole in the dielectric layer. Patterning the hole is accomplished at least in part by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material. A phase change feature is then formed in contact with the dielectric layer such that a portion of the phase change feature at least partially fills the hole in the dielectric layer. At least a portion of the patterned dielectric layer remains in the ultimate memory cell.

摘要翻译： 通过形成电介质层并在电介质层中构图孔来制造存储单元。 至少部分地通过在有效去除与催化材料接触的电介质层的那些区域的条件下在反应物存在下使介电层与催化材料接触来对孔进行图案化。 然后形成与电介质层接触的相变特征，使得相变特征的一部分至少部分地填充介电层中的孔。 图案化介电层的至少一部分保留在最终存储单元中。