公开(公告)号：US20060264036A1

公开(公告)日：2006-11-23

申请号：US11491816

申请日：2006-07-24

Applicant: Shyng-Tsong Chen ,  Stefanie Chiras ,  Matthew Colburn ,  Tomothy Dalton ,  Jeffrey Hedrick ,  Elbert Huang ,  Kaushik Kumar ,  Michael Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Robert Rosenberg ,  Christy Tyberg ,  Roy Yu

Inventor： Shyng-Tsong Chen ,  Stefanie Chiras ,  Matthew Colburn ,  Tomothy Dalton ,  Jeffrey Hedrick ,  Elbert Huang ,  Kaushik Kumar ,  Michael Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Robert Rosenberg ,  Christy Tyberg ,  Roy Yu

IPC: H01L21/4763

CPC classification number: H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

Abstract translation: 在多电平微电子集成电路中，空气包括永久线路电介质，超低K材料通过电介质。 在通过清洁热分解除去牺牲材料并通过IC结构中的孔隙率辅助副产物扩散后，将空气供应到线路电平。 任选地，空气也包括在通孔级电介质中的孔隙中。 通过将空气结合到本发明产生的程度，使层内和层间介电值最小化。

公开(公告)号：US06986975B2

公开(公告)日：2006-01-17

申请号：US10818099

申请日：2004-04-05

Applicant: Sidlgata V. Sreenivasan ,  Byung J. Choi ,  Matthew Colburn ,  Todd Bailey

Inventor： Sidlgata V. Sreenivasan ,  Byung J. Choi ,  Matthew Colburn ,  Todd Bailey

IPC: G03F9/00

CPC classification number: B29C35/0888 ,  B29C37/0053 ,  B29C43/003 ,  B29C43/021 ,  B29C2035/0827 ,  B29C2043/025 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  G03F9/00 ,  Y10S101/36 ,  Y10T428/24802

Abstract: The present invention includes a method of determining an alignment between a substrate and a template spaced-apart from the substrate and having a distance defined therebetween, the substrate having a first pattern disposed thereon and the template having a second pattern disposed thereon, the method including, sensing the first and the second pattern, with the distance being established such that the first and the second pattern form a desired moiré pattern when the template and the substrate are in a desired spatial relationship.

Abstract translation: 本发明包括一种确定衬底和与衬底间隔开的并具有在其间限定的距离的模板之间的对准的方法，所述衬底具有设置在其上的第一图案，并且所述模板具有设置在其上的第二图案，所述方法包括 感测第一和第二图案，其中建立距离使得当模板和衬底处于期望的空间关系时，第一和第二图案形成期望的莫尔图案。

公开(公告)号：US20050272341A1

公开(公告)日：2005-12-08

申请号：US11150059

申请日：2005-06-10

Applicant: Matthew Colburn ,  Satyanarayana Nitta ,  Sampath Purushothaman

Inventor： Matthew Colburn ,  Satyanarayana Nitta ,  Sampath Purushothaman

IPC: H01J9/14 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a low k, ultra-low k, and extreme-low k multilayer interconnect structure on a substrate in which the interconnect line features are separated laterally by a dielectric with vertically oriented nano-scale voids formed by perforating it using sub-optical lithography patterning and etching techniques and closing off the tops of the perforations by a dielectric deposition step. The lines are supported either by solid or patterned dielectric features underneath. The method avoids the issues associated with the formation of air gaps after the fabrication of conductor patterns and those associated with the integration of conventional low k, ultra-low k and extreme low k dielectrics which have porosity present before the formation of the interconnect patterns.

Abstract translation: 一种用于在衬底上制造低k，超低k和极低k多层互连结构的方法，其中互连线特征由具有垂直取向的纳米级空隙的电介质侧向分开， 光刻图案和蚀刻技术，并通过介电沉积步骤封闭穿孔的顶部。 线路由固体或图案化的电介质特征支撑。 该方法避免了在形成导体图案之后与形成气隙相关的问题，以及与形成互连图案之前具有孔隙率的常规低k，超低k和极低k电介质的集成相关联的问题。

公开(公告)号：US06954275B2

公开(公告)日：2005-10-11

申请号：US09920341

申请日：2001-08-01

Applicant: Byung J. Choi ,  Matthew Colburn ,  S. V. Sreenivasan ,  C. Grant Willson ,  Todd Bailey ,  John Ekerdt

Inventor： Byung J. Choi ,  Matthew Colburn ,  S. V. Sreenivasan ,  C. Grant Willson ,  Todd Bailey ,  John Ekerdt

IPC: G01B11/14 ,  B29C31/04 ,  B29C35/08 ,  B29C43/02 ,  B29C59/02 ,  G03F7/00 ,  G03F7/20 ,  G03F9/00 ,  H01L21/027

CPC classification number: B29C43/021 ,  B29C31/045 ,  B29C31/047 ,  B29C35/0888 ,  B29C43/003 ,  B29C59/022 ,  B29C2035/0827 ,  B29C2037/90 ,  B29C2043/025 ,  B29D11/0023 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  G03F9/00

Abstract: Described are high precision gap and orientation measurement methods between a template and a substrate used in imprint lithography processes. Gap and orientation measurement methods presented here include uses of broad-band light based measuring techniques.

Abstract translation: 描述了在压印光刻工艺中使用的模板和衬底之间的高精度间隙和取向测量方法。 这里介绍的差距和方向测量方法包括使用宽带光基测量技术。

公开(公告)号：US20050202350A1

公开(公告)日：2005-09-15

申请号：US10799282

申请日：2004-03-13

Applicant: Matthew Colburn ,  Kenneth Carter ,  Gary McClelland ,  Dirk Pfeiffer

Inventor： Matthew Colburn ,  Kenneth Carter ,  Gary McClelland ,  Dirk Pfeiffer

IPC: B29C33/38 ,  G03F7/00 ,  H01L21/768

CPC classification number: G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/76807 ,  H01L21/76817 ,  H01L2924/0002 ,  Y10S425/81 ,  Y10T428/16 ,  Y10T428/24851 ,  Y10T428/31504 ,  H01L2924/00

Abstract: The process of producing a dual damascene structure used for the interconnect architecture of semiconductor chips. More specifically the use of imprint lithography to fabricate dual damascene structures in a dielectric and the fabrication of dual damascene structured molds.

Abstract translation: 制造用于半导体芯片的互连架构的双镶嵌结构的过程。 更具体地说，使用压印光刻法在电介质中制造双镶嵌结构以及制造双镶嵌结构的模具。

公开(公告)号：US06919152B2

公开(公告)日：2005-07-19

申请号：US10445863

申请日：2003-05-27

Applicant: S. V. Sreenivasan ,  Byung J. Choi ,  Matthew Colburn ,  Todd Bailey

Inventor： S. V. Sreenivasan ,  Byung J. Choi ,  Matthew Colburn ,  Todd Bailey

IPC: G02B5/18 ,  B29C35/08 ,  B29C37/00 ,  G03F7/00 ,  G03F7/20 ,  H01L21/027 ,  G03F9/00 ,  G03B17/00

CPC classification number: B29C35/0888 ,  B29C37/0053 ,  B29C43/003 ,  B29C43/021 ,  B29C2035/0827 ,  B29C2043/025 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  G03F9/00 ,  Y10S101/36 ,  Y10T428/24802

Abstract: A system of determining and correcting alignment during imprint lithography process is described. During an imprint lithographic process the template may be aligned with the substrate by the use of alignment marks disposed on both the template and substrate. The alignment may be determined and corrected for before the layer is processed.

Abstract translation: 描述了在压印光刻工艺期间确定和校正对准的系统。 在压印光刻工艺期间，模板可以通过使用设置在模板和衬底上的对准标记与衬底对准。 可以在层被处理之前确定和校正对准。

公开(公告)号：US06916585B2

公开(公告)日：2005-07-12

申请号：US10446192

申请日：2003-05-27

Applicant: Sidlgata V. Sreenivasan ,  Byung J. Choi ,  Matthew Colburn ,  Todd Bailey

Inventor： Sidlgata V. Sreenivasan ,  Byung J. Choi ,  Matthew Colburn ,  Todd Bailey

IPC: G02B5/18 ,  B29C35/08 ,  B29C37/00 ,  G03F7/00 ,  G03F7/20 ,  H01L21/027 ,  G03F9/00 ,  G03C5/00

CPC classification number: B29C35/0888 ,  B29C37/0053 ,  B29C43/003 ,  B29C43/021 ,  B29C2035/0827 ,  B29C2043/025 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  G03F9/00 ,  Y10S101/36 ,  Y10T428/24802

Abstract: A method of determining and correcting alignment during imprint lithography process is described. During an imprint lithographic process the template may be aligned with the substrate by the use of alignment marks disposed on both the template and substrate. The alignment may be determined and corrected for before the layer is processed.

Abstract translation: 描述了在压印光刻工艺期间确定和校正对准的方法。 在压印光刻工艺期间，模板可以通过使用设置在模板和衬底上的对准标记与衬底对准。 可以在层被处理之前确定和校正对准。

公开(公告)号：US20050079719A1

公开(公告)日：2005-04-14

申请号：US10683333

申请日：2003-10-10

Applicant: Matthew Colburn ,  Satya Nitta ,  Sampath Purushothaman ,  Charles Black ,  Kathryn Guarini

Inventor： Matthew Colburn ,  Satya Nitta ,  Sampath Purushothaman ,  Charles Black ,  Kathryn Guarini

IPC: H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L23/52 ,  H05K3/10 ,  H05K3/46

CPC classification number: H01L21/31144 ,  H01L21/7682 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.

Abstract translation: 描述了一种形成具有纳米柱状金属间电介质的互连结构的方法，涉及使用固体电介质构造互连结构，并通过模板形成和蚀刻引入垂直排列的纳米尺度孔的规则阵列以形成孔阵列并随后夹紧 具有盖电介质的孔阵列的顶部。 还描述了构建多层纳米柱状互连结构的方法和方法的变化。

公开(公告)号：US06696220B2

公开(公告)日：2004-02-24

申请号：US09976681

申请日：2001-10-12

Applicant: Todd Bailey ,  Byung J. Choi ,  Matthew Colburn ,  S. V. Sreenivasan ,  C. Grant Willson ,  John Ekerdt

Inventor： Todd Bailey ,  Byung J. Choi ,  Matthew Colburn ,  S. V. Sreenivasan ,  C. Grant Willson ,  John Ekerdt

IPC: G03C176

CPC classification number: G11B5/855 ,  B29C35/0888 ,  B29C37/0053 ,  B29C43/003 ,  B29C2035/0827 ,  B29C2043/025 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  G03F9/00 ,  Y10S977/887

Abstract: Described are imprint lithography templates, methods of forming and using the templates, and a template holder device. An imprint lithography template may include a body with a plurality of recesses on a surface of the body. The body may be of a material that is substantially transparent to activating light. At least a portion of the plurality of recesses may define features having a feature size less than about 250 nm. A template may be formed by obtaining a material that is substantially transparent to activating light and forming a plurality or recesses on a surface of the template. In some embodiments, a template may further include at least one alignment mark. In some embodiments, a template may further include a gap sensing area. An imprint lithography template may be used to form an imprinted layer in a light curable liquid disposed on a substrate. During use, the template may be disposed within a template holder. The template holder may include a body with an opening configured to receive the template, a support plate, and at least one piezo actuator coupled to the body. The piezo actuator may be configured to alter a physical dimension of the template during use.

Abstract translation: 描述了压印光刻模板，形成和使用模板的方法以及模板保持装置。 压印光刻模板可以包括在主体的表面上具有多个凹部的主体。 身体可以是对于激活光是基本上透明的材料。 多个凹部的至少一部分可以限定具有小于约250nm的特征尺寸的特征。 可以通过获得对于激活光而基本上透明并在模板的表面上形成多个或多个凹陷的材料来形成模板。 在一些实施例中，模板还可以包括至少一个对准标记。 在一些实施例中，模板还可以包括间隙感测区域。 可以使用压印光刻模板来在设置在基板上的可光固化液体中形成印刷层。 在使用期间，模板可以设置在模板保持器内。 模板保持器可以包括具有构造成接收模板的开口的主体，支撑板和耦合到主体的至少一个压电致动器。 压电致动器可以被配置为在使用期间改变模板的物理尺寸。

公开(公告)号：US20080038915A1

公开(公告)日：2008-02-14

申请号：US11849048

申请日：2007-08-31

Applicant: Daniel EDELSTEIN ,  Matthew COLBURN ,  Edward COONEY ,  Timothy DALTON ,  John FITZSIMMONS ,  Jeffrey GAMBINO ,  Elbert HUANG ,  Michael LANE ,  Vincent MCGAHAY ,  Lee NICHOLSON ,  Satyanarayana NITTA ,  Sampath PURUSHOTHAMAN ,  Sujatha SANKARAN ,  Thomas SHAW ,  Andrew SIMON ,  Anthony STAMPER

Inventor： Daniel EDELSTEIN ,  Matthew COLBURN ,  Edward COONEY ,  Timothy DALTON ,  John FITZSIMMONS ,  Jeffrey GAMBINO ,  Elbert HUANG ,  Michael LANE ,  Vincent MCGAHAY ,  Lee NICHOLSON ,  Satyanarayana NITTA ,  Sampath PURUSHOTHAMAN ,  Sujatha SANKARAN ,  Thomas SHAW ,  Andrew SIMON ,  Anthony STAMPER

IPC: H01L21/4763

CPC classification number: B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: Semiconductor structure includes an insulator layer having at least one interconnect feature and at least one gap formed in the insulator layer spanning more than a minimum spacing of interconnects.

Abstract translation: 半导体结构包括具有至少一个互连特征的绝缘体层和形成在绝缘体层中的至少一个间隙，跨越多于互连的最小间隔。