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    MUSHROOM TYPE MEMORY CELL HAVING SELF-ALIGNED BOTTOM ELECTRODE AND DIODE ACCESS DEVICE
    5.
    发明申请
    MUSHROOM TYPE MEMORY CELL HAVING SELF-ALIGNED BOTTOM ELECTRODE AND DIODE ACCESS DEVICE 审中-公开
    具有自对准底部电极和二极管访问装置的MUSHROOM型存储单元

    公开(公告)号：US20100019215A1

    公开(公告)日：2010-01-28

    申请号：US12177435

    申请日：2008-07-22

    申请人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Thomas D. Happ ,  Matthew J. Breitwisch ,  Alejandro Gabriel Schrott ,  Min Yang

    发明人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Thomas D. Happ ,  Matthew J. Breitwisch ,  Alejandro Gabriel Schrott ,  Min Yang

    IPC分类号： H01L47/00 ,  H01L21/00

    CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

    摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein includes a plurality of word lines extending in a first direction, and a plurality of bit lines overlying the plurality of word lines and extending in a second direction. A plurality of memory cells are at cross-point locations. Each memory cell comprises a diode having first and second sides aligned with sides of a corresponding word line. Each memory cell also includes a bottom electrode self-centered on the diode, the bottom electrode having a top surface with a surface area less than that of the top surface of the diode. Each of the memory cells includes a strip of memory material on the top surface of the bottom electrode, the strip of memory material underlying and in electrical communication with a corresponding bit line.

    摘要翻译： 描述存储器件以及制造方法。 如本文所述的存储器件包括沿第一方向延伸的多个字线和覆盖多个字线并沿第二方向延伸的多个位线。 多个存储单元处于交叉点位置。 每个存储单元包括具有与相应字线的侧面对准的第一和第二侧的二极管。 每个存储单元还包括以二极管为中心的底部电极，底部电极具有表面积小于二极管顶表面的顶表面。 每个存储器单元包括在底部电极的顶表面上的存储器材料条，存储器材料条下面并与相应位线电连通。

    Phase change memory cell with limited switchable volume
    6.
    发明授权
    Phase change memory cell with limited switchable volume 失效
    相变容量有限的相变存储单元

    公开(公告)号：US07514705B2

    公开(公告)日：2009-04-07

    申请号：US11410466

    申请日：2006-04-25

    申请人： Matthew J. Breitwisch ,  Chung Hon Lam ,  Jan Boris Philipp ,  Stephen M. Rossnagel ,  Alejandro Gabriel Schrott

    发明人： Matthew J. Breitwisch ,  Chung Hon Lam ,  Jan Boris Philipp ,  Stephen M. Rossnagel ,  Alejandro Gabriel Schrott

    IPC分类号： H01L47/00

    CPC分类号： H01L45/144 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1625 ,  H01L45/1666

    摘要： A memory cell comprises a dielectric layer and a phase change material. The dielectric layer defines a trench having both a wide portion and a narrow portion. The narrow portion is substantially narrower than the wide portion. The phase change material, in turn, at least partially fills the wide and narrow portions of the trench. What is more, the phase change material within the narrow portion of the trench defines a void. Data can be stored in the memory cell by heating the phase change material by applying a pulse of switching current to the memory cell. Advantageously, embodiments of the invention provide high switching current density and heating efficiency so that the magnitude of the switching current pulse can be reduced.

    摘要翻译： 存储单元包括介电层和相变材料。 电介质层限定了具有宽部分和窄部分的沟槽。 狭窄部分基本上比宽部分窄。 相变材料又至少部分地填充沟槽的宽而窄的部分。 此外，沟槽狭窄部分内的相变材料限定了空隙。 通过向存储单元施加切换电流的脉冲来加热相变材料，可以将数据存储在存储单元中。 有利地，本发明的实施例提供高开关电流密度和加热效率，从而可以减小开关电流脉冲的幅度。

    Phase change memory cell array with self-converged bottom electrode and method for manufacturing
    9.
    发明授权
    Phase change memory cell array with self-converged bottom electrode and method for manufacturing 有权
    具有自会聚底电极的相变存储单元阵列及其制造方法

    公开(公告)号：US08178386B2

    公开(公告)日：2012-05-15

    申请号：US11855983

    申请日：2007-09-14

    申请人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Matthew J. Breitwisch

    发明人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Matthew J. Breitwisch

    IPC分类号： H01L21/06

    CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

    摘要： An array of phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming a patterning layer on the separation layer and forming an array of mask openings in the patterning layer using lithographic process. Etch masks are formed within the mask openings by a process that compensates for variation in the size of the mask openings that result from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings exposing the underlying contacts. Electrode material is deposited within the electrode openings; and memory elements are formed over the bottom electrodes. Finally, bit lines are formed over the memory elements to complete the memory cells. In the resulting memory array, the critical dimension of the top surface of bottom electrode varies less than the width of the memory elements in the mask openings.

    摘要翻译： 通过在触点阵列上形成分离层，在分离层上形成图形层并使用光刻工艺在图案形成层中形成掩模开口阵列来制造相变存储器单元的阵列。 通过补偿由平版印刷工艺产生的掩模开口的尺寸变化的过程，在掩模开口内形成蚀刻掩模。 蚀刻掩模用于蚀刻通过分离层以限定暴露下面的触点的电极开口的阵列。 电极材料沉积在电极开口内; 并且存储元件形成在底部电极上。 最后，在存储器元件上形成位线以完成存储器单元。 在所得到的存储器阵列中，底部电极的顶表面的临界尺寸小于掩模开口中存储元件的宽度。

    SELF-ALIGNED BIT LINE UNDER WORD LINE MEMORY ARRAY
    10.
    发明申请
    SELF-ALIGNED BIT LINE UNDER WORD LINE MEMORY ARRAY 有权
    自动对齐的位线在字线内存阵列下

    公开(公告)号：US20110305074A1

    公开(公告)日：2011-12-15

    申请号：US12815680

    申请日：2010-06-15

    申请人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Erh-Kun Lai ,  Matthew J. Breitwisch

    发明人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Erh-Kun Lai ,  Matthew J. Breitwisch

    IPC分类号： G11C11/00 ,  H01L45/00 ,  H01L21/82

    CPC分类号： H01L27/2454 ,  H01L27/2445 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

    摘要： A memory device is described that comprises a plurality of bit lines and an array of vertical transistors arranged on the plurality of bit lines. A plurality of word lines is formed along rows of vertical transistors in the array which comprise thin film sidewalls of word line material and arranged so that the thin film sidewalls merge in the row direction, and do not merge in the column direction, to form word lines. The word lines provide “surrounding gate” structures for embodiments in which the vertical transistors are field effect transistors. Memory elements are formed in electrical communication with the vertical transistors. A fully self-aligned process is provided in which the word lines and memory elements are aligned with the vertical transistors without additional patterning steps.

    摘要翻译： 描述了包括多个位线和布置在多个位线上的垂直晶体管阵列的存储器件。 多个字线沿阵列中的垂直晶体管行形成，其中包括字线材料的薄膜侧壁，并且布置成使得薄膜侧壁在行方向上合并，并且不在列方向上合并，以形成字 线条。 对于其中垂直晶体管是场效应晶体管的实施例，字线提供“周围栅极”结构。 存储元件形成为与垂直晶体管电连通。 提供了完全自对准的工艺，其中字线和存储元件与垂直晶体管对准，而没有额外的图案化步骤。