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180 条记录 (耗时 0.028 秒)

    CMOS fabricated on different crystallographic orientation substrates
    61.
    发明申请
    CMOS fabricated on different crystallographic orientation substrates 审中-公开
    CMOS制造在不同的晶体取向基板上

    公开(公告)号：US20050224797A1

    公开(公告)日：2005-10-13

    申请号：US10816562

    申请日：2004-04-01

    申请人： Chih-Hsin Ko ,  Wen-Chin Lee

    发明人： Chih-Hsin Ko ,  Wen-Chin Lee

    IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/04

    CPC分类号： H01L29/045 ,  H01L21/76264 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84

    摘要： A microelectronic device including a first substrate bonded to a second substrate. The first and second substrate may have different crystallographic orientations. The first substrate includes an opening through which an epitaxially grown portion of the second substrate extends. A first semiconductor device is coupled to the first substrate. A second semiconductor device is coupled to the epitaxially grown portion of the second substrate.

    摘要翻译： 一种微电子器件，包括接合到第二衬底的第一衬底。 第一和第二基底可以具有不同的晶体取向。 第一衬底包括第二衬底的外延生长部分延伸通过的开口。 第一半导体器件耦合到第一衬底。 第二半导体器件耦合到第二衬底的外延生长部分。

    Strained channel complementary field-effect transistors and methods of manufacture
    62.
    发明申请
    Strained channel complementary field-effect transistors and methods of manufacture 有权
    应变通道互补场效应晶体管及其制造方法

    公开(公告)号：US20050035470A1

    公开(公告)日：2005-02-17

    申请号：US10639170

    申请日：2003-08-12

    申请人： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chenming Hu

    发明人： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chenming Hu

    IPC分类号： H01L21/8238 ,  H01L27/088

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848

    摘要： A transistor includes a gate dielectric overlying a channel region. A source region and a drain region are located on opposing sides of the channel region. The channel region is formed from a first semiconductor material and the source and drain regions are formed from a second semiconductor material. A gate electrode overlies the gate dielectric. A pair of spacers is formed on sidewalls of the gate electrode. Each of the spacers includes a void adjacent the channel region. A high-stress film can overlie the gate electrode and spacers.

    摘要翻译： 晶体管包括覆盖沟道区的栅极电介质。 源极区域和漏极区域位于沟道区域的相对侧上。 沟道区由第一半导体材料形成，源极和漏极区由第二半导体材料形成。 栅极电极覆盖栅极电介质。 在栅电极的侧壁上形成一对间隔物。 每个间隔件包括邻近通道区域的空隙。 高应力膜可以覆盖栅电极和间隔物。

    Forming embedded dielectric layers adjacent to sidewalls of shallow trench isolation regions
    64.
    发明授权
    Forming embedded dielectric layers adjacent to sidewalls of shallow trench isolation regions 有权
    形成与浅沟槽隔离区域的侧壁相邻的嵌入电介质层

    公开(公告)号：US07928474B2

    公开(公告)日：2011-04-19

    申请号：US11839352

    申请日：2007-08-15

    申请人： Hong-Nien Lin ,  Chih-Hsin Ko ,  Wen-Chin Lee

    发明人： Hong-Nien Lin ,  Chih-Hsin Ko ,  Wen-Chin Lee

    IPC分类号： H01L21/02

    CPC分类号： H01L29/7833 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

    摘要： A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate; an insulating region extending from substantially a top surface of the semiconductor substrate into the semiconductor substrate; an embedded dielectric spacer adjacent the insulating region, wherein a bottom of the embedded dielectric spacer adjoins the semiconductor substrate; and a semiconductor material adjoining a top edge and extending on a sidewall of the embedded dielectric spacer.

    摘要翻译： 提供半导体结构。 半导体结构包括半导体衬底; 绝缘区域，其从所述半导体衬底的大致顶表面延伸到所述半导体衬底中; 邻近所述绝缘区域的嵌入式电介质间隔件，其中所述嵌入式电介质间隔件的底部邻接所述半导体衬底; 以及邻接在顶部边缘并且在嵌入的电介质间隔物的侧壁上延伸的半导体材料。

    Strained channel complementary field-effect transistors
    65.
    发明授权
    Strained channel complementary field-effect transistors 有权
    应变通道互补场效应晶体管

    公开(公告)号：US07442967B2

    公开(公告)日：2008-10-28

    申请号：US11407633

    申请日：2006-04-20

    申请人： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chenming Hu

    发明人： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chenming Hu

    IPC分类号： H01L31/0328

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848

    摘要： A transistor includes a gate dielectric overlying a channel region. A source region and a drain region are located on opposing sides of the channel region. The channel region is formed from a first semiconductor material and the source and drain regions are formed from a second semiconductor material. A gate electrode overlies the gate dielectric. A pair of spacers is formed on sidewalls of the gate electrode. Each of the spacers includes a void adjacent the channel region. A high-stress film can overlie the gate electrode and spacers.

    摘要翻译： 晶体管包括覆盖沟道区的栅极电介质。 源极区域和漏极区域位于沟道区域的相对侧上。 沟道区由第一半导体材料形成，源极和漏极区由第二半导体材料形成。 栅极电极覆盖栅极电介质。 在栅电极的侧壁上形成一对间隔物。 每个间隔件包括邻近通道区域的空隙。 高应力膜可以覆盖栅电极和间隔物。

    Forming Embedded Dielectric Layers Adjacent to Sidewalls of Shallow Trench Isolation Regions
    69.
    发明申请
    Forming Embedded Dielectric Layers Adjacent to Sidewalls of Shallow Trench Isolation Regions 有权
    形成与浅沟槽隔离区侧壁相邻的嵌入式电介质层

    公开(公告)号：US20090045411A1

    公开(公告)日：2009-02-19

    申请号：US11839352

    申请日：2007-08-15

    申请人： Hong-Nien Lin ,  Chih-Hsin Ko ,  Wen-Chin Lee

    发明人： Hong-Nien Lin ,  Chih-Hsin Ko ,  Wen-Chin Lee

    IPC分类号： H01L29/24 ,  H01L29/778

    CPC分类号： H01L29/7833 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

    摘要： A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate; an insulating region extending from substantially a top surface of the semiconductor substrate into the semiconductor substrate; an embedded dielectric spacer adjacent the insulating region, wherein a bottom of the embedded dielectric spacer adjoins the semiconductor substrate; and a semiconductor material adjoining a top edge and extending on a sidewall of the embedded dielectric spacer.

    摘要翻译： 提供半导体结构。 半导体结构包括半导体衬底; 绝缘区域，其从所述半导体衬底的大致顶表面延伸到所述半导体衬底中; 邻近所述绝缘区域的嵌入式电介质间隔件，其中所述嵌入式电介质间隔件的底部邻接所述半导体衬底; 以及邻接在顶部边缘并且在嵌入的电介质间隔物的侧壁上延伸的半导体材料。

    Offset spacer formation for strained channel CMOS transistor
    70.
    发明授权
    Offset spacer formation for strained channel CMOS transistor 有权
    用于应变通道CMOS晶体管的偏移间隔物形成

    公开(公告)号：US07321155B2

    公开(公告)日：2008-01-22

    申请号：US10840911

    申请日：2004-05-06

    申请人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ge

    发明人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ge

    IPC分类号： H01L29/772

    CPC分类号： H01L29/7845 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  Y10S257/90

    摘要： A strained channel transistor and method for forming the same, the strained channel transistor including a semiconductor substrate; a gate dielectric overlying a channel region; a gate electrode overlying the gate dielectric; source drain extension (SDE) regions and source and drain (S/D) regions; wherein a stressed dielectric portion selected from the group consisting of a pair of stressed offset spacers disposed adjacent the gate electrode and a stressed dielectric layer disposed over the gate electrode including the S/D regions is disposed to exert a strain on a channel region.

    摘要翻译： 应变沟道晶体管及其形成方法，所述应变沟道晶体管包括半导体衬底; 覆盖沟道区的栅极电介质; 覆盖栅极电介质的栅电极; 源极扩展（SDE）区域和源极和漏极（S / D）区域; 其特征在于，设置有选自由邻近所述栅电极配置的一对应力偏置间隔物和设置在包括所述S / D区域的所述栅极上方的应力介电层的应力电介质部分，以在沟道区域上施加应变。