公开(公告)号：US20120275252A1

公开(公告)日：2012-11-01

申请号：US13456020

申请日：2012-04-25

申请人： Richard Ferrant ,  Roland Thewes

发明人： Richard Ferrant ,  Roland Thewes

IPC分类号： G11C7/12 ,  G11C7/02

CPC分类号： G11C7/065 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2211/4016

摘要： A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line (BL) and an input connected to a second bit line complementary to the first bit line and a second CMOS inverter having an output connected to the second bit line (/BL) and an input connected to the first bit line. Each CMOS inverter includes pull-up and pull-down transistors, wherein the sources of either of the pull-up transistors or the pull-down transistors are electrically coupled and connected to a pull-up voltage source or a pull-down voltage source without an intermediate transistor between the sources of the transistors and the voltage source.

摘要翻译： 一种用于感测存储在存储单元阵列的多个存储单元中的数据的差分读出放大器，包括连接到第一位线（BL）的输出的第一CMOS反相器和连接到与第一位线互补的第二位线的输入端 位线和具有连接到第二位线（/ BL）的输出的第二CMOS反相器和连接到第一位线的输入。 每个CMOS反相器包括上拉和下拉晶体管，其中上拉晶体管或下拉晶体管中的任一个的源极电耦合并连接到上拉电压源或下拉电压源，而没有 在晶体管的源极和电压源之间的中间晶体管。

公开(公告)号：US08223582B2

公开(公告)日：2012-07-17

申请号：US12793553

申请日：2010-06-03

申请人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

发明人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C11/4085 ,  G11C2211/4016

摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.

摘要翻译： 在绝缘体上半导体衬底上制成的电路。 该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域 在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。 每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。 晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

公开(公告)号：US20110170343A1

公开(公告)日：2011-07-14

申请号：US12942754

申请日：2010-11-09

申请人： Carlos Mazure ,  Richard Ferrant

发明人： Carlos Mazure ,  Richard Ferrant

IPC分类号： G11C11/40 ,  H01L29/786

CPC分类号： H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/0711 ,  H01L27/10802 ,  H01L29/086 ,  H01L29/7302

摘要： The invention relates to a memory cell having an FET transistor with a source, a drain and a floating body between the source and the drain, and an injector that can be controlled to inject a charge into the floating body of the FET transistor. The injector includes a bipolar transistor having an emitter, a base and a collector formed by the body of the FET transistor. Specifically, in the memory cell, the emitter of the bipolar transistor is arranged so that the source of the FET transistor serves as the base for the bipolar transistor. The invention also includes a memory array comprising a plurality of memory cells according to the first aspect of the invention, and to methods of controlling such memory cells.

摘要翻译： 本发明涉及具有源极，漏极和源极和漏极之间的浮体的FET晶体管的存储单元，以及可以被控制以将电荷注入到FET晶体管的浮动体中的注入器。 注射器包括具有由FET晶体管的主体形成的发射极，基极和集电极的双极晶体管。 具体地说，在存储单元中，双极型晶体管的发射极配置成使FET晶体管的源极作为双极晶体管的基极。 本发明还包括包括根据本发明的第一方面的多个存储器单元的存储器阵列以及控制这种存储器单元的方法。

公开(公告)号：US20110170327A1

公开(公告)日：2011-07-14

申请号：US12974916

申请日：2010-12-21

申请人： Carlos Mazure ,  Richard Ferrant

发明人： Carlos Mazure ,  Richard Ferrant

IPC分类号： G11C15/04 ,  H01L27/12

CPC分类号： G11C15/046 ,  H04L45/7453

摘要： The invention provides a content-addressable memory cell formed by two transistors that are configured so that one of the transistors is for storing a data bit and the other for is storing the complement of the data bit. Each transistor has a back control gate that can be controlled to block the associated transistor. The device also includes a comparison circuit that is configured to operate the first and second transistors in read mode while controlling the back control gate of each of the transistors so as to block the passing transistor if a proposed bit and the stored bit correspond. Then, the presence or absence of current on a source line linked to the source of each of the transistors indicates whether the proposed bit and the stored bit are identical or not. The invention also provides methods for operating the content-addressable memory cells of this invention, as well as content-addressable memories having a plurality of the content-addressable memory cells of this invention.

摘要翻译： 本发明提供一种由两个晶体管形成的可内容寻址的存储单元，其被配置为使晶体管中的一个用于存储数据位，而另一个用于存储数据位的补码。 每个晶体管具有可控制的阻挡相关晶体管的反向控制栅极。 该器件还包括比较电路，其被配置为在读取模式下操作第一和第二晶体管，同时控制每个晶体管的反向控制栅极，以便如果所提出的位和存储的位对应，则阻止通过晶体管。 然后，连接到每个晶体管的源极的源极线上的电流的存在或不存在指示所提出的位和存储的位是否相同。 本发明还提供了用于操作本发明的内容可寻址存储器单元的方法，以及具有多个本发明的可内容寻址存储单元的可内容寻址存储器。

公开(公告)号：US20110133776A1

公开(公告)日：2011-06-09

申请号：US12961293

申请日：2010-12-06

申请人： Carlos Mazure ,  Richard Ferrant

发明人： Carlos Mazure ,  Richard Ferrant

IPC分类号： H03K19/173 ,  H01L27/12 ,  H03K3/01

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/11807

摘要： This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate and including an array of patterns, each pattern being formed by at least one field-effect transistor, each FET transistor having, in the thin film, a source region, a drain region, a channel region, and a front control gate region formed above the channel region. The provided device further includes at least one FET transistor having a pattern including a back control gate region formed in the base substrate beneath the channel region, the back gate region being capable of being biased in order to shift the threshold voltage of the transistor to simulate a modification in the channel width of the transistor or to force the transistor to remain off or on whatever the voltage applied on its front control gate. This invention also provides methods of operating such semiconductor device structures.

摘要翻译： 本发明提供了一种半导体器件结构，其形成在传统的绝缘体上半导体（SeOI）衬底上并且包括一组图案，每个图案由至少一个场效应晶体管形成，每个FET晶体管在薄膜中， 源极区域，漏极区域，沟道区域和形成在沟道区域上方的前部控制栅极区域。 所提供的器件还包括至少一个FET晶体管，其具有包括形成在沟道区域下方的基底衬底中的反向控制栅极区域的图案，所述背栅极区域能够被偏置以便移位晶体管的阈值电压以模拟 晶体管的沟道宽度的修改或迫使晶体管保持关断或者在其前控制栅上施加的任何电压。 本发明还提供了操作这种半导体器件结构的方法。

公开(公告)号：US07817466B2

公开(公告)日：2010-10-19

申请号：US12130918

申请日：2008-05-30

申请人： Richard Ferrant ,  Franck Genevaux ,  David Burnett ,  Gerald Gouya ,  Pierre Malinge

发明人： Richard Ferrant ,  Franck Genevaux ,  David Burnett ,  Gerald Gouya ,  Pierre Malinge

IPC分类号： G11C11/34

CPC分类号： H01L27/105 ,  G11C11/4023 ,  G11C11/4026 ,  G11C11/405 ,  G11C2211/4016 ,  H01L21/8232 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10882 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/118 ,  H01L27/11803 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/7841

摘要： A semiconductor array includes a matrix of cells, the matrix being arranged in rows and columns of cells, and a plurality of control lines. Each cell is coupled to a number of control lines allowing to select and read/write said cell. At least one of said control lines is coupled to cells of a plurality of columns and of at least two rows of the matrix.

摘要翻译： 半导体阵列包括单元矩阵，矩阵以单元格的行和列排列，以及多个控制线。 每个单元耦合到许多控制线，允许选择和读取/写入所述单元。 所述控制线中的至少一个耦合到多个列和至少两行矩阵的单元。

公开(公告)号：US20090125789A1

公开(公告)日：2009-05-14

申请号：US12140643

申请日：2008-06-17

申请人： Richard Ferrant ,  Cedric Maufront

发明人： Richard Ferrant ,  Cedric Maufront

IPC分类号： G06F11/10

CPC分类号： H04L25/14 ,  H04L1/0043 ,  H04L2001/0094

摘要： A data bus including a plurality of logic blocks coupled in series, each logic block including at least one buffer for buffering at least one data bit transmitted via the data bus and at least one of the logic blocks further including circuitry coupled in parallel with the at least one buffer and arranged to determine a first bit of error correction code associated with the at least one data bit.

摘要翻译： 包括串联耦合的多个逻辑块的数据总线，每个逻辑块包括用于缓冲经由数据总线传输的至少一个数据位的至少一个缓冲器，以及至少一个逻辑块，还包括与该数据总线并联耦合的电路 至少一个缓冲器，并被布置成确定与所述至少一个数据位相关联的纠错码的第一位。

公开(公告)号：US20090086535A1

公开(公告)日：2009-04-02

申请号：US12130918

申请日：2008-05-30

申请人： Richard Ferrant ,  Franck Genevaux ,  David Burnett ,  Gerald Gouya ,  Pierre Malinge

发明人： Richard Ferrant ,  Franck Genevaux ,  David Burnett ,  Gerald Gouya ,  Pierre Malinge

IPC分类号： G11C11/34

CPC分类号： H01L27/105 ,  G11C11/4023 ,  G11C11/4026 ,  G11C11/405 ,  G11C2211/4016 ,  H01L21/8232 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10882 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/118 ,  H01L27/11803 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/7841

摘要： A semiconductor array includes a matrix of cells, the matrix being arranged in rows and columns of cells, and a plurality of control lines. Each cell is coupled to a number of control lines allowing to select and read/write said cell. At least one of said control lines is coupled to cells of a plurality of columns and of at least two rows of the matrix.

摘要翻译： 半导体阵列包括单元矩阵，矩阵以单元格的行和列排列，以及多个控制线。 每个单元耦合到许多控制线，允许选择和读取/写入所述单元。 所述控制线中的至少一个耦合到多个列和至少两行矩阵的单元。

公开(公告)号：US07180801B2

公开(公告)日：2007-02-20

申请号：US10745294

申请日：2003-12-23

申请人： Richard Ferrant ,  François Jacquet ,  Laurent Murillo

发明人： Richard Ferrant ,  François Jacquet ,  Laurent Murillo

IPC分类号： G11C7/00

CPC分类号： G11C29/848 ,  G11C29/808

摘要： An integrated circuit memory including at least two banks each provided with an array of storage elements having at least one redundancy column and each associated with specific sense amplifiers, a row of input/output buffer circuits common to the memory banks, and for each memory bank, a circuit for assigning the redundancy column to an input/output line connected to one of said buffers. The assigning can be performed, for a line of current rank, towards the columns of preceding rank and towards the columns of following rank.

摘要翻译： 一种集成电路存储器，包括至少两个存储体，每个存储体具有存储元件的阵列，所述存储元件阵列具有至少一个冗余列，并且每个与特定读出放大器相关联，每行与存储体共用的输入/输出缓冲器电路行以及每个存储体 ，用于将冗余列分配给连接到所述缓冲器之一的输入/输出线的电路。 对于当前秩的行，可以针对前一列的列和朝向下一列的列执行分配。

公开(公告)号：US07130206B2

公开(公告)日：2006-10-31

申请号：US10955836

申请日：2004-09-30

申请人： Richard Ferrant

发明人： Richard Ferrant

IPC分类号： G11C15/00 ,  G11C11/00

CPC分类号： G11C13/0004 ,  G11C15/02 ,  G11C15/046

摘要： A content addressable memory cell is described. In one embodiment, the content addressable memory cell includes first and second resistive memory elements being coupled in a first series connection and being connected between a first potential value and a second potential value being smaller than said first potential value, and means for their switching between states exhibiting different electric resistance values. The memory cell includes a first field effect transistor and a second field effect transistor, said first and second transistors having drain-source-paths and gate electrodes, said drain-source-paths of said first and second transistors being connected in a second series connection and being connected to at least one of first current lines. The first current line is connected to a potential value level detector for sensing a potential difference as to said third potential value.

摘要翻译： 描述内容可寻址存储器单元。 在一个实施例中，内容可寻址存储器单元包括第一和第二电阻存储器元件，其以第一串联连接耦合并连接在第一电位值和小于所述第一电位值的第二电位值之间， 呈现不同电阻值的状态。 存储单元包括第一场效应晶体管和第二场效应晶体管，所述第一和第二晶体管具有漏源路径和栅电极，所述第一和第二晶体管的所述漏源极路径以第二串联连接 并且连接到第一电流线中的至少一个。 第一电流线连接到电位值电平检测器，用于感测关于所述第三电位值的电位差。