公开(公告)号：US08681976B2

公开(公告)日：2014-03-25

申请号：US13106268

申请日：2011-05-12

申请人： Conrad Sauerwald ,  Joseph P. Bratt ,  Joshua Phillips de Cesare ,  Timothy John Millet ,  Weihua Mao

发明人： Conrad Sauerwald ,  Joseph P. Bratt ,  Joshua Phillips de Cesare ,  Timothy John Millet ,  Weihua Mao

IPC分类号： H04L29/06

CPC分类号： H04L9/0863 ,  H04L9/0866

摘要： Disclosed herein are systems, methods, and non-transitory computer-readable storage media for generating a device dependent cryptographic key in a rate-limited way. A system configured to practice the method first receives data associated with a user. The data associated with the user can be a password, a personal identification number (PIN), or a hash of the password. Then the system performs a first encryption operation on the user data based on a device-specific value to yield first intermediate data and performs a second encryption operation on the first intermediate data based on the device-specific value to yield second intermediate data. Then the system iteratively repeats the second encryption operation until a threshold is met, wherein each second encryption operation is performed on the second intermediate data from a previous second encryption operation. The iterations produce a final cryptographic key which the system can then output or use for a cryptographic operation.

摘要翻译： 本文公开了用于以速率限制的方式生成依赖于设备的加密密钥的系统，方法和非暂时的计算机可读存储介质。 被配置为练习该方法的系统首先接收与用户相关联的数据。 与用户相关联的数据可以是密码，个人识别码（PIN）或密码的散列。 然后，系统基于设备特定值对用户数据执行第一加密操作，以产生第一中间数据，并且基于设备特定值对第一中间数据执行第二加密操作以产生第二中间数据。 然后，系统迭代地重复第二加密操作，直到满足阈值，其中从先前的第二加密操作对第二中间数据执行每个第二加密操作。 迭代产生最终的加密密钥，系统然后可以输出或用于加密操作。

公开(公告)号：US20130322753A1

公开(公告)日：2013-12-05

申请号：US13485421

申请日：2012-05-31

申请人： Suk Hwan Lim ,  D. Amnon Silverstein ,  Guy Cote ,  Steven David Hordley ,  Graham Finlayson ,  Weichun Ku ,  Joseph P. Bratt

发明人： Suk Hwan Lim ,  D. Amnon Silverstein ,  Guy Cote ,  Steven David Hordley ,  Graham Finlayson ,  Weichun Ku ,  Joseph P. Bratt

IPC分类号： G06T5/00

CPC分类号： G06T5/001 ,  G06K9/38 ,  G06T1/20 ,  G06T5/002 ,  G06T5/003 ,  G06T5/008 ,  G06T5/50 ,  G06T2207/10024 ,  G06T2207/20012 ,  G06T2207/20028 ,  G06T2207/20208

摘要： Systems and methods for local tone mapping are provided. In one example, an electronic device includes an electronic display, an imaging device, and an image signal processor. The electronic display may display images of a first bit depth, and the imaging device may include an image sensor that obtains image data of a higher bit depth than the first bit depth. The image signal processor may process the image data, and may include local tone mapping logic that may apply a spatially varying local tone curve to a pixel of the image data to preserve local contrast when displayed on the display. The local tone mapping logic may smooth the local tone curve applied to the intensity difference between the pixel and another nearby pixel exceeds a threshold.

公开(公告)号：US08525895B2

公开(公告)日：2013-09-03

申请号：US12846008

申请日：2010-07-29

申请人： Guy Côté ,  Jeffrey E. Frederiksen ,  Joseph P. Bratt

发明人： Guy Côté ,  Jeffrey E. Frederiksen ,  Joseph P. Bratt

IPC分类号： H04N5/228 ,  H04N9/64 ,  G06K9/00

CPC分类号： G06T3/4015

摘要： Various techniques for applying binning compensation filtering to binned raw image data acquired by an image sensor are provided. In one embodiment, a binning compensation filter (BCF) includes separate digital differential analyzers (DDA) for vertical and horizontal scaling. A current position of an output pixel is determined by incrementing the DDA based upon a step size. Using the known output pixel position, a center source input pixel and an index corresponding to the between-pixel fractional position of the output pixel position relative to the input pixels may be selected for filtering. Using the selected center input pixel, one or more same-colored neighboring source pixels may be selected. The number of selected source pixels may depend on the number of taps used by the scaling logic, and may depend on whether horizontal or vertical scaling is being applied. Using the selected index, a set of filter coefficients may be selected from a filter coefficient lookup table, applied to the selected source pixels, and the results may be summed to determine a value for an output pixel having a position corresponding to the current position of the DDA. This process may be repeated for each input pixel and may be performed in both vertical and horizontal directions, thus ultimately producing a re-sampled set of image data that is spatially evenly distributed.

摘要翻译： 提供了用于将分档补偿滤波应用于由图像传感器获取的二进制原始图像数据的各种技术。 在一个实施例中，分箱补偿滤波器（BCF）包括用于垂直和水平缩放的单独的数字差分分析器（DDA）。 通过基于步长增加DDA来确定输出像素的当前位置。 使用已知的输出像素位置，可以选择中心源输入像素和对应于输出像素位置相对于输入像素的像素间分数位置的索引用于滤波。 使用所选择的中心输入像素，可以选择一个或多个相同颜色的相邻源像素。 选择的源像素的数量可以取决于缩放逻辑使用的抽头的数量，并且可以取决于是否应用水平或垂直缩放。 使用所选择的索引，可以从应用于所选择的源像素的滤波器系数查找表中选择一组滤波器系数，并且将结果相加以确定具有对应于当前位置的位置的输出像素的值 DDA。 对于每个输入像素可以重复该过程，并且可以在垂直和水平方向上执行该过程，从而最终产生在空间上均匀分布的重新采样的图像数据集。

公开(公告)号：US08508621B2

公开(公告)日：2013-08-13

申请号：US12895346

申请日：2010-09-30

申请人： Guy Côté ,  Jeffrey E. Frederiksen ,  Joseph P. Bratt ,  Jung Wook Cho

发明人： Guy Côté ,  Jeffrey E. Frederiksen ,  Joseph P. Bratt ,  Jung Wook Cho

IPC分类号： H04N5/76

CPC分类号： H04N5/772 ,  H04N5/23229 ,  H04N5/23235 ,  H04N5/2354 ,  H04N5/3572 ,  H04N5/367 ,  H04N9/045 ,  H04N9/735 ,  H04N19/80

摘要： Certain embodiments of the present disclosure provide a flexible memory input/output controller that is configured to the storing and reading of multiple types of pixels and pixel memory formats. For instance, the memory I/O controller may support the storing and reading of raw image pixels at various bits of precision, such as 8-bit, 10-bit, 12-bit, 14-bit, and 16-bit. Pixel formats that are unaligned with memory bytes (e.g., not being a multiple of 8-bits) may be stored in a packed manner. The memory I/O controller may also support various formats of RGB pixel sets and YCC pixel sets.

摘要翻译： 本公开的某些实施例提供了一种灵活的存储器输入/输出控制器，其被配置为存储和读取多种类型的像素和像素存储器格式。 例如，存储器I / O控制器可以支持以各种精度位（例如8位，10位，12位，14位和16位）存储和读取原始图像像素。 与存储器字节不对齐的像素格式（例如，不是8位的倍数）可以以打包的方式存储。 存储器I / O控制器还可以支持RGB像素集和YCC像素集的各种格式。

公开(公告)号：US08405668B2

公开(公告)日：2013-03-26

申请号：US12950293

申请日：2010-11-19

申请人： Joseph P. Bratt ,  Peter F. Holland

发明人： Joseph P. Bratt ,  Peter F. Holland

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F12/10

CPC分类号： G06F12/0215 ,  G06F12/0802 ,  G06F12/0862 ,  G06F12/1027 ,  G06F12/123 ,  G06F2212/302 ,  G06F2212/654

摘要： In an embodiment, a display pipe includes one or more translation units corresponding to images that the display pipe is reading for display. Each translation unit may be configured to prefetch translations ahead of the image data fetches, which may prevent translation misses in the display pipe (at least in most cases). The translation units may maintain translations in first-in, first-out (FIFO) fashion, and the display pipe fetch hardware may inform the translation unit when a given translation or translation is no longer needed. The translation unit may invalidate the identified translations and prefetch additional translation for virtual pages that are contiguous with the most recently prefetched virtual page.

公开(公告)号：US20120127364A1

公开(公告)日：2012-05-24

申请号：US12950185

申请日：2010-11-19

申请人： Joseph P. Bratt ,  Peter F. Holland

发明人： Joseph P. Bratt ,  Peter F. Holland

IPC分类号： H04N7/01

CPC分类号： H04N9/67 ,  G09G2340/06

摘要： A display pipe may include a video pipe outputting pixels of a video stream in a first color space, e.g. YCbCr color space. The display pipe may also include a first color space converter to convert the output pixels to a second color space, e.g. to RGB color space, producing a conversion output in which some of the converted output pixels have values that are invalid pixel values in the second color space. The display pipe may also include a blend unit that performs blending operations in the second color space on the converted output pixels to produce a blended conversion output that includes blended pixels in the second color space. A second color space converter in the display pipe may convert the blended pixels from the second color space to the first color space, and correctly display the converted blended pixels on a display screen.

摘要翻译： 显示管可以包括输出第一颜色空间中的视频流的像素的视频管，例如。 YCbCr颜色空间。 显示管还可以包括第一颜色空间转换器，以将输出像素转换为第二颜色空间，例如， 到RGB颜色空间，产生转换输出，其中一些转换的输出像素具有在第二颜色空间中的无效像素值的值。 显示管还可以包括混合单元，其在转换的输出像素上的第二颜色空间中执行混合操作，以产生包括第二颜色空间中的混合像素的混合转换输出。 显示管中的第二颜色空间转换器可以将混合像素从第二颜色空间转换为第一颜色空间，并将转换的混合像素正确显示在显示屏上。

公开(公告)号：US20120026368A1

公开(公告)日：2012-02-02

申请号：US12846008

申请日：2010-07-29

申请人： Guy Côté ,  Jeffrey E. Frederiksen ,  Joseph P. Bratt

发明人： Guy Côté ,  Jeffrey E. Frederiksen ,  Joseph P. Bratt

IPC分类号： H04N9/64

CPC分类号： G06T3/4015

摘要： Various techniques for applying binning compensation filtering to binned raw image data acquired by an image sensor are provided. In one embodiment, a binning compensation filter (BCF) includes separate digital differential analyzers (DDA) for vertical and horizontal scaling. A current position of an output pixel is determined by incrementing the DDA based upon a step size. Using the known output pixel position, a center source input pixel and an index corresponding to the between-pixel fractional position of the output pixel position relative to the input pixels may be selected for filtering. Using the selected center input pixel, one or more same-colored neighboring source pixels may be selected. The number of selected source pixels may depend on the number of taps used by the scaling logic, and may depend on whether horizontal or vertical scaling is being applied. Using the selected index, a set of filter coefficients may be selected from a filter coefficient lookup table, applied to the selected source pixels, and the results may be summed to determine a value for an output pixel having a position corresponding to the current position of the DDA. This process may be repeated for each input pixel and may be performed in both vertical and horizontal directions, thus ultimately producing a re-sampled set of image data that is spatially evenly distributed.

摘要翻译： 提供了用于将分档补偿滤波应用于由图像传感器获取的二进制原始图像数据的各种技术。 在一个实施例中，分箱补偿滤波器（BCF）包括用于垂直和水平缩放的单独的数字差分分析器（DDA）。 通过基于步长增加DDA来确定输出像素的当前位置。 使用已知的输出像素位置，可以选择中心源输入像素和对应于输出像素位置相对于输入像素的像素间分数位置的索引用于滤波。 使用所选择的中心输入像素，可以选择一个或多个相同颜色的相邻源像素。 选择的源像素的数量可以取决于缩放逻辑使用的抽头的数量，并且可以取决于是否应用水平或垂直缩放。 使用所选择的索引，可以从应用于所选择的源像素的滤波器系数查找表中选择一组滤波器系数，并且将结果相加以确定具有对应于当前位置的位置的输出像素的值 DDA。 对于每个输入像素可以重复该过程，并且可以在垂直和水平方向上执行该过程，从而最终产生在空间上均匀分布的重新采样的图像数据集。

公开(公告)号：US07653776B2

公开(公告)日：2010-01-26

申请号：US11304439

申请日：2005-12-14

申请人： William P. Cornelius ,  Paul A. Baker ,  Joseph P. Bratt

发明人： William P. Cornelius ,  Paul A. Baker ,  Joseph P. Bratt

IPC分类号： G06F3/00 ,  G06F13/00

CPC分类号： G06F1/22

摘要： A system that selectively couples one or more IC chips to card slots. The system contains a Z-bar switch which includes: a select input; a first IC port coupled to a first IC pin; a second IC port coupled to a second IC pin; a first card slot port coupled to a first card slot pin; and a second card slot port coupled to a second card slot pin. If the select input receives a first control pattern, the Z-bar switch is configured to: couple the first IC port to the first card slot port; and to couple the second IC port to the second card slot port. If the select input receives a second control pattern, the Z-bar switch is configured to: couple the first IC port to the second card slot port; leave the second IC port floating; and to leave the first card slot port floating.

摘要翻译： 将一个或多个IC芯片选择性地耦合到卡插槽的系统。 该系统包含一个Z-bar开关，它包括：一个选择输入; 耦合到第一IC引脚的第一IC端口; 耦合到第二IC引脚的第二IC端口; 耦合到第一卡槽销的第一卡槽口; 以及耦合到第二卡槽销的第二卡槽口。 如果选择输入接收到第一控制模式，则Z-bar开关被配置为：将第一IC端口耦合到第一卡插槽端口; 并将第二IC端口耦合到第二卡槽口。 如果选择输入接收到第二控制模式，则Z-bar开关被配置为：将第一IC端口耦合到第二卡插槽端口; 离开第二个IC端口; 并离开第一个卡槽口浮动。

公开(公告)号：US07114058B1

公开(公告)日：2006-09-26

申请号：US10038383

申请日：2001-12-31

申请人： Sushma Shrikant Trivedi ,  Joseph P. Bratt ,  Jack Benkual ,  Ronald Ray Hochsprung ,  Derek Fujio Iwamoto

发明人： Sushma Shrikant Trivedi ,  Joseph P. Bratt ,  Jack Benkual ,  Ronald Ray Hochsprung ,  Derek Fujio Iwamoto

IPC分类号： G06F9/30

CPC分类号： G06F9/3853 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867 ,  G06F9/3879 ,  G06F9/3885

摘要： Methods and apparatuses for dispatching instructions executed by at least one functional unit of a data processor, each one of the instructions having a corresponding priority number, in a data processing system having at least one host processor with host processor cache and host memory are described herein. In one aspect of the invention, an exemplary method includes receiving a next instruction from an instruction stream, examining a current instruction group to determine if the current instruction group is completed, adding the next instruction to the current instruction group if the current instruction group is not completed, and dispatching the current instruction group if the current instruction group is completed.

摘要翻译： 本文描述了在具有至少一个具有主处理器高速缓存和主机存储器的主机处理器的数据处理系统中调度由数据处理器的至少一个功能单元执行的指令的方法和装置，每个指令具有相应的优先级号码 。 在本发明的一个方面，一种示例性方法包括从指令流接收下一条指令，检查当前指令组以确定当前指令组是否完成，如果当前指令组是 未完成，如果当前指令组完成，则调度当前指令组。

公开(公告)号：US06822654B1

公开(公告)日：2004-11-23

申请号：US10038700

申请日：2001-12-31

申请人： Sushma Shrikant Trivedi ,  Joseph P. Bratt ,  Jack Benkual ,  Vaughn Todd Arnold ,  Yutaka Takahashi ,  Steven Todd Weybrew ,  Derek Fujio Iwamoto ,  David Ligon

发明人： Sushma Shrikant Trivedi ,  Joseph P. Bratt ,  Jack Benkual ,  Vaughn Todd Arnold ,  Yutaka Takahashi ,  Steven Todd Weybrew ,  Derek Fujio Iwamoto ,  David Ligon

IPC分类号： G06F1314

CPC分类号： G06F13/1668

摘要： At least one chip of a chipset in a computer system having at least one host processor and a host memory are described herein. In one aspect of the invention, an exemplary chip includes an interconnect, a memory interface coupled to the interconnect, the memory interface providing access to the host memory and controlling memory refresh and memory access, a host interface coupled to the interconnect, the host interface providing access to the host processor, and a programmable media processor coupled to the interconnect, the media processor accessing the host through the host interface and the media processor accessing the host memory through the memory interface, wherein the media processor processes time based media.

摘要翻译： 本文中描述了具有至少一个主机处理器和主机存储器的计算机系统中的芯片组的至少一个芯片。 在本发明的一个方面中，示例性芯片包括互连，耦合到互连的存储器接口，存储器接口，提供对主机存储器的访问和控制存储器刷新和存储器访问，耦合到互连的主机接口，主机接口 提供对主处理器的访问，以及耦合到互连的可编程媒体处理器，媒体处理器通过主机接口访问主机，并且媒体处理器通过存储器接口访问主机存储器，其中媒体处理器处理基于时间的媒体。