公开(公告)号：US20050254221A1

公开(公告)日：2005-11-17

申请号：US11190561

申请日：2005-07-26

申请人： Ravindranath Kollipara ,  David Nguyen ,  Belgacem Haba

发明人： Ravindranath Kollipara ,  David Nguyen ,  Belgacem Haba

IPC分类号： G06F13/40 ,  G11C5/00 ,  H05K1/02 ,  H05K1/11 ,  H05K1/14 ,  H05K7/06 ,  H05K7/14

CPC分类号： G11C5/04 ,  G06F13/409 ,  G11C5/00 ,  H05K1/023 ,  H05K1/117 ,  H05K1/141 ,  H05K1/147 ,  H05K1/148 ,  H05K7/1459 ,  H05K2201/10189

摘要： The terminating module includes integrated circuits and a termination circuit which receive clock signals from the integrated circuit. The integrated circuit includes at least one memory integrated circuit mounted on a printed circuit board. An electrical connector is configured to couple the terminating module to a motherboard. Additionally, the termination circuit includes a resistor. In another embodiment, the terminating module provides a printed circuit board, a memory integrated circuit mounted on the circuit board, a terminator circuit which includes a resistor, and an electrical connector. The electrical connector couples the terminating module to a motherboard

摘要翻译： 终端模块包括集成电路和从集成电路接收时钟信号的终端电路。 集成电路包括安装在印刷电路板上的至少一个存储器集成电路。 电连接器被配置为将终端模块耦合到主板。 另外，终端电路包括电阻器。 在另一个实施例中，端接模块提供印刷电路板，安装在电路板上的存储器集成电路，包括电阻器和电连接器的终端电路。 电连接器将终端模块耦合到主板

公开(公告)号：US06898085B2

公开(公告)日：2005-05-24

申请号：US10695854

申请日：2003-10-30

申请人： Belgacem Haba ,  Richard E. Perego ,  David Nguyen ,  Billy W. Garrett, Jr. ,  Ely Tsern ,  Craig E. Hampel ,  Wai-Yeung Yip

发明人： Belgacem Haba ,  Richard E. Perego ,  David Nguyen ,  Billy W. Garrett, Jr. ,  Ely Tsern ,  Craig E. Hampel ,  Wai-Yeung Yip

IPC分类号： G06F13/40 ,  G11C5/00 ,  H05K1/02 ,  H05K1/11 ,  H05K1/14 ,  H05K7/06 ,  H05K7/14 ,  H05K7/02 ,  H05K7/10

CPC分类号： G11C5/04 ,  G06F13/409 ,  G11C5/00 ,  H05K1/023 ,  H05K1/117 ,  H05K1/141 ,  H05K1/147 ,  H05K1/148 ,  H05K7/1459 ,  H05K2201/10189

摘要： Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.

公开(公告)号：US09112498B2

公开(公告)日：2015-08-18

申请号：US13568976

申请日：2012-08-07

申请人： Yong Li ,  Fuqiang Shi ,  Andrew Kwok-Cheung Lee ,  David Nguyen ,  Jiang Chen

发明人： Yong Li ,  Fuqiang Shi ,  Andrew Kwok-Cheung Lee ,  David Nguyen ,  Jiang Chen

IPC分类号： H02M3/335 ,  H02M1/08 ,  H03K17/16

CPC分类号： H03K17/166 ,  H02M1/08 ,  H02M3/335 ,  H02M3/33523 ,  H03K17/163

摘要： The embodiments herein describe a dynamic metal-oxide-semiconductor field-effect transistor (MOSFET) gate driver system architecture and control scheme. The MOSFET gate driver system dynamically adjusts both the gate driver turn-on-resistance and the gate driver turn-off resistance within a single (i.e., one) switching cycle to reduce electromagnetic interference (EMI) in the system and to minimize the conduction loss of a power MOSFET during operation.

摘要翻译： 本文的实施例描述了动态金属氧化物半导体场效应晶体管（MOSFET）栅极驱动器系统架构和控制方案。 MOSFET栅极驱动器系统在单个（即一个）开关周期内动态地调节栅极驱动器导通电阻和栅极驱动器关断电阻，以减少系统中的电磁干扰（EMI）并使传导损耗最小化 的功率MOSFET。

公开(公告)号：US08874656B2

公开(公告)日：2014-10-28

申请号：US13307451

申请日：2011-11-30

申请人： Paul O'Connell ,  David Nguyen ,  George White ,  Matt Crist ,  Michael Tuccinard ,  Matthew Stuehler ,  Michael Novak

发明人： Paul O'Connell ,  David Nguyen ,  George White ,  Matt Crist ,  Michael Tuccinard ,  Matthew Stuehler ,  Michael Novak

IPC分类号： G06F15/16

CPC分类号： G06Q40/06

摘要： A finds comparison tool is provided that includes a presentation tier providing a plurality of interfaces for interacting with a plurality of client applications. The presentation tier allows the client applications to send requests for a plurality of analytics to be performed regarding comparing the performance of one or more funds or portfolios as well allowing mobile-based client applications and web-based client applications to communicate with the funds comparison tool. An application tier processes the requests sent by the client applications by providing the data used by the client applications, storing and retrieving of session data, and an interface for the analytics information captured during sessions so as to allow a visualization of the analytics used in the comparison of the one or more funds or portfolios.

摘要翻译： 提供了一种查找比较工具，其包括提供用于与多个客户端应用程序交互的多个界面的表示层。 表示层允许客户端应用程序发送关于比较一个或多个资金或组合的性能的多个分析请求，并允许基于移动的客户端应用程序和基于Web的客户端应用程序与资金比较工具进行通信 。 应用程序层通过提供客户端应用程序使用的数据，存储和检索会话数据以及用于在会话期间捕获的分析信息的界面来处理客户端应用程序发送的请求，以便允许可视化在 比较一个或多个基金或投资组合。

公开(公告)号：US08560797B2

公开(公告)日：2013-10-15

申请号：US13421701

申请日：2012-03-15

申请人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasborro ,  David Nguyen

发明人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasborro ,  David Nguyen

IPC分类号： G06F12/00

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit, over a first plurality of wires, to the DRAM a first code to indicate that first data is to be written to the DRAM and a column address to indicate a column location of a memory core in the DRAM where the first data is to be written. The interface is further to transmit a second code to indicate whether mask information for the first data will be sent to the DRAM. If the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are sent after the second code is sent. The interface is further to transmit to the DRAM, over a second plurality of wires separate from the first plurality of wires, the first data.

摘要翻译： 一种用于控制动态随机存取存储器（DRAM）的装置，该装置包括一个接口，用于在第一组多条引线上向DRAM发送一个第一代码，以指示第一个数据要写入DRAM，列地址 以指示要写入第一数据的DRAM中的存储器核的列位置。 该接口还用于发送第二代码以指示是否将第一数据的掩码信息发送到DRAM。 如果第二代码指示将发送掩码信息，则在发送第二代码之后发送列地址的一部分和掩码信息的一部分。 接口进一步通过与第一多个电线分开的第二多个电线将DRAM发送到第一数据。

公开(公告)号：USRE44019E1

公开(公告)日：2013-02-19

申请号：US12605303

申请日：2009-10-23

申请人： Thomas F. Fox ,  Sayeh Khalili ,  Belgacem Haba ,  David Nguyen ,  Richard Warmke ,  Xingchao Yuan

发明人： Thomas F. Fox ,  Sayeh Khalili ,  Belgacem Haba ,  David Nguyen ,  Richard Warmke ,  Xingchao Yuan

IPC分类号： H01L21/00

CPC分类号： G11C5/02 ,  G11C5/04 ,  G11C29/08 ,  G11C2029/4402 ,  H01L23/5382 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable to identify the integrated circuit dice that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dice and the programmable memory device. The integrated circuit dice of the plurality of integrated circuit dice that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dice.

摘要翻译： 提供了半导体模块，其包括半导体外壳和位于壳体内的多个集成电路芯片。 半导体模块还包括位于壳体内的电可耦合到多个集成电路芯片的可编程存储器件。 可编程存储器件可编程以识别满足预定标准（例如工作频率要求或核心定时等级）的集成电路芯片。 此外，提供了一种用于访问半导体模块的方法。 提供上述壳体以包围多个集成电路芯片和可编程存储器件。 然后识别满足预定标准的多个集成电路芯片的集成电路芯片。 随后编程可编程存储器件以识别所选择的集成电路芯片。

公开(公告)号：US20120176820A1

公开(公告)日：2012-07-12

申请号：US13086290

申请日：2011-04-13

申请人： Yong Li ,  Fuqiang Shi ,  Xiaolin Gao ,  David Nguyen

发明人： Yong Li ,  Fuqiang Shi ,  Xiaolin Gao ,  David Nguyen

IPC分类号： H02M3/335

CPC分类号： H02M3/33507 ,  H02M2001/0035 ,  Y02B70/16

摘要： A switch controller is disclosed that adaptively controls the operating frequency of a switching power converter in order to improve one-time load response and repetitive dynamic load responses. During a transition from a high load to low load condition, the switch controller clamps the operating frequency of the switching power converter at an intermediate frequency for a period of time before allowing the operating frequency to return to a frequency associated with the low load condition. The clamped frequency is higher than the frequency associated with the low load condition thereby allowing improved response to a subsequent load change to a high load condition. Thus, the system improves dynamic load response without compromising no-load power consumption.

摘要翻译： 公开了一种开关控制器，其自适应地控制开关功率转换器的工作频率，以便改善一次负载响应和重复的动态负载响应。 在从高负载到低负载状态的转变期间，开关控制器将开关功率转换器的工作频率在中间频率之前的一段时间内进行钳位，然后允许工作频率返回到与低负载状态相关联的频率。 钳位频率高于与低负载条件相关的频率，从而允许改进对后续负载变化对高负载状态的响应。 因此，该系统可以改善动态负载响应，而不会影响空载功耗。

公开(公告)号：US08043099B1

公开(公告)日：2011-10-25

申请号：US11866927

申请日：2007-10-03

申请人： Jim Chin-Nan Ni ,  David Nguyen ,  David Q. Chow ,  Frank I-Kang Yu ,  Abraham C. Ma ,  Ming-Shiang Shen

发明人： Jim Chin-Nan Ni ,  David Nguyen ,  David Q. Chow ,  Frank I-Kang Yu ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC分类号： H01R13/44

CPC分类号： G06K19/07732 ,  H05K5/0278

摘要： An extended universal serial bus (USB) storage device is described herein. According to one embodiment, an extended USB storage device includes a printed circuit board assembly (PCBA) having a flash memory device and a flash controller mounted thereon, and an extended USB connector plug coupled to the PCBA for providing a USB compatible interface between an external device and the flash memory device and the flash controller, wherein the extended USB connector plug includes a first end used to couple to the external device and a second end coupled to the flash memory device and the flash controller. The extended USB connector plug includes multiple communication interfaces. Other methods and apparatuses are also described.

摘要翻译： 本文描述了扩展通用串行总线（USB）存储设备。 根据一个实施例，扩展的USB存储设备包括具有闪存设备和安装在其上的闪存控制器的印刷电路板组件（PCBA），以及耦合到PCBA的扩展USB连接器插头，用于在外部 设备和闪存设备和闪存控制器，其中扩展的USB连接器插头包括用于耦合到外部设备的第一端和耦合到闪存设备和闪存控制器的第二端。 扩展的USB连接器插头包括多个通信接口。 还描述了其它方法和装置。

公开(公告)号：US08019958B2

公开(公告)日：2011-09-13

申请号：US12875483

申请日：2010-09-03

申请人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarre ,  David Nguyen

发明人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarre ,  David Nguyen

IPC分类号： G06F12/00

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： In a method of controlling a memory device, the following is conveyed over a first set of interconnect resources: a first command that specifies activation of a row of memory cells; a second command that specifies a write operation, wherein write data is written to the row; a bit that specifies whether precharging occurs after the write data is written; and a code that specifies whether data mask information will be issued for the write operation. If the code specifies that the information will be issued, then the information, which specifies whether to selectively write portions of the write data, is conveyed over the first set of interconnect resources after conveying the code. The write data to be written in connection with the write operation is conveyed over a second set of interconnect resources that is separate from the first set of interconnect resources.

摘要翻译： 在控制存储器件的方法中，以下是通过第一组互连资源传送的：指定一行存储器单元的激活的第一命令; 指定写操作的第二命令，其中写数据被写入行; 指定在写入数据写入之后是否发生预充电的一点; 以及指定是否将为写入操作发布数据掩码信息的代码。 如果代码指定信息将被发出，则在传送代码之后，通过第一组互连资源传送指定是否选择性地写入写入数据的部分的信息。 要写入与写入操作相关的写入数据通过与第一组互连资源分开的第二组互连资源传送。

公开(公告)号：US08014130B1

公开(公告)日：2011-09-06

申请号：US11950190

申请日：2007-12-04

申请人： David Nguyen ,  Nan Nan ,  Abraham C. Ma ,  Jim Chin-Nan Ni ,  Charles Chung Lee ,  Ming-Shiang Shen

发明人： David Nguyen ,  Nan Nan ,  Abraham C. Ma ,  Jim Chin-Nan Ni ,  Charles Chung Lee ,  Ming-Shiang Shen

IPC分类号： H02B1/00

CPC分类号： H01R13/629 ,  H01R13/447 ,  H05K5/0278

摘要： Various embodiments of a USB drive pen device are disclosed herein. In one embodiment, a USB drive pen device includes a USB plug assembly having a flash controller and a flash memory device, a pusher assembly including a rotator having one or more tabs disposed thereon, and a housing for housing at least a portion of the USB plug assembly and the pusher assembly. The housing includes a tunnel and an inner tube extended from the tunnel disposed within the housing. An intersection between the tunnel and inner tube includes one or more angled corners to lock the USB plug assembly in either a deployed position or a retracted position. Other methods and apparatuses are also described.

摘要翻译： 这里公开了USB驱动笔装置的各种实施例。 在一个实施例中，USB驱动笔装置包括具有闪光灯控制器和闪存装置的USB插头组件，包括其上设置有一个或多个接头的旋转器的推动器组件和用于容纳USB的至少一部分的壳体 插头组件和推动器组件。 壳体包括隧道和从设置在壳体内的隧道延伸的内管。 隧道和内管之间的交叉点包括一个或多个成角度的角部，以将USB插头组件锁定在展开位置或缩回位置。 还描述了其它方法和装置。