公开(公告)号：US20050167717A1

公开(公告)日：2005-08-04

申请号：US11080032

申请日：2005-03-14

申请人： Won-Suk Yang ,  Sang-Hoo Song ,  Ki-Nam Kim ,  Hong-Sik Jeong

发明人： Won-Suk Yang ,  Sang-Hoo Song ,  Ki-Nam Kim ,  Hong-Sik Jeong

IPC分类号： H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L27/10894 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/10882 ,  H01L2924/0002 ,  H01L2924/00

摘要： A conductive portion connects a lower conductive layer formed on a semiconductor substrate provided in a first interlayer insulating layer to an upper conductive layer formed on the lower conductive layer, and provided in a second interlayer insulating layer. This portion is divided into at least one plug and a pad. At least one plug is formed in a first interlayer insulating layer and the lower part of a second interlayer insulating layer. The second interlayer insulating layer is divided into a plurality of interlayer insulating layers so that upper and lower widths of the divided plugs formed in the divided portion of the second interlayer insulating layer are not greatly different from each other. The pad formed on the upper portion of the second interlayer insulating layer has an upper width such that the upper conductive layer connected to the pad is not undesirably connected to an adjacent upper conductive layer via the pad.

摘要翻译： 导电部分将形成在第一层间绝缘层中的半导体衬底上形成的下导电层连接到形成在下导电层上的上导电层，并设置在第二层间绝缘层中。 该部分被分成至少一个插头和垫。 在第一层间绝缘层和第二层间绝缘层的下部形成至少一个插塞。 第二层间绝缘层被分成多个层间绝缘层，使得形成在第二层间绝缘层的分割部分中的分隔插塞的上下宽度彼此不是很大的不同。 形成在第二层间绝缘层的上部的焊盘具有上部宽度，使得连接到焊盘的上部导电层不会通过焊盘不期望地连接到相邻的上部导电层。

公开(公告)号：US06911362B2

公开(公告)日：2005-06-28

申请号：US10635195

申请日：2003-08-06

申请人： Ki-Nam Kim ,  Yoon-Jong Song ,  Heung-Jin Joo

发明人： Ki-Nam Kim ,  Yoon-Jong Song ,  Heung-Jin Joo

IPC分类号： H01L27/105 ,  H01L21/8246 ,  H01L27/115 ,  H01L21/8242

CPC分类号： H01L27/11502 ,  H01L27/11507

摘要： Methods for forming an electronic device can include forming a capacitor structure on a portion of a substrate with the capacitor structure including a first electrode on the substrate, a capacitor dielectric on the first electrode, a second electrode on the dielectric, and a hard mask on the second electrode. More particularly, the capacitor dielectric can be between the first and second electrodes, the first electrode and the capacitor dielectric can be between the second electrode and the substrate, and the first and second electrodes and the capacitor dielectric can be between the hard mask and the substrate. An interlayer dielectric layer can be formed on the hard mask and on portions of the substrate surrounding the capacitor structure, and portions of the interlayer dielectric layer can be removed to expose the hard mask while maintaining portions of the interlayer dielectric layer on portions of the substrate surrounding the capacitor structure. The hard mask can then be removed thereby exposing portions of the second electrode while maintaining the portions of the interlayer dielectric layer on portions of the substrate surrounding the capacitor.

摘要翻译： 用于形成电子器件的方法可以包括在衬底的一部分上形成电容器结构，其中电容器结构包括在衬底上的第一电极，第一电极上的电容器电介质，电介质上的第二电极， 第二电极。 更具体地，电容器电介质可以在第一和第二电极之间，第一电极和电容器电介质可以在第二电极和衬底之间，并且第一和第二电极和电容器电介质可以在硬掩模和第二电极之间 基质。 可以在硬掩模和围绕电容器结构的基板的部分上形成层间电介质层，并且可以去除层间介电层的部分以暴露硬掩模，同时将层间电介质层的部分保持在基板的部分上 围绕电容器结构。 然后可以去除硬掩模，从而暴露第二电极的部分，同时保持层间电介质层的部分在包围电容器的基板的部分上。

公开(公告)号：US20050035384A1

公开(公告)日：2005-02-17

申请号：US10948610

申请日：2004-09-23

申请人： Hyun-Ho Kim ,  Dong-Jin Jung ,  Ki-Nam Kim ,  Sang-Don Nam ,  Kyu-Mann Lee

发明人： Hyun-Ho Kim ,  Dong-Jin Jung ,  Ki-Nam Kim ,  Sang-Don Nam ,  Kyu-Mann Lee

IPC分类号： H01L27/105 ,  G11C11/22 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/76

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L27/11507

摘要： A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of rows and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes. Ferroelectric capacitors in adjacent rows may share a common ferroelectric dielectric region. Related fabrication methods are discussed.

公开(公告)号：US06844583B2

公开(公告)日：2005-01-18

申请号：US10136991

申请日：2002-05-02

申请人： Hyun-Ho Kim ,  Dong-Jin Jung ,  Ki-Nam Kim ,  Sang-Don Nam ,  Kyu-Mann Lee

发明人： Hyun-Ho Kim ,  Dong-Jin Jung ,  Ki-Nam Kim ,  Sang-Don Nam ,  Kyu-Mann Lee

IPC分类号： H01L27/105 ,  G11C11/22 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L27/11507

摘要： A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of rows and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes. Ferroelectric capacitors in adjacent rows may share a common ferroelectric dielectric region. Related fabrication methods are discussed.

摘要翻译： 铁电存储器件包括微电子衬底和在衬底上的多个铁电电容器，其被布置为在行和列方向上的多个行和列。 多个平行板线覆盖在铁电电容器上并沿着行方向延伸，其中板线在至少两个相邻行中接触铁电电容器。 多个板线可以包括多个局部板线，并且铁电存储器件还可以包括设置在局部板线上的绝缘层和设置在绝缘层上的多个主板线，并且使本地板线通过 绝缘层中的开口。 在一些实施例中，相邻行中的铁电电容器共享公共上电极，并且各自的局部板线设置在相应的公共上电极上。 相邻行中的铁电电容器可以共享公共铁电电介质区域。 讨论相关的制造方法。

公开(公告)号：US06496426B2

公开(公告)日：2002-12-17

申请号：US09884536

申请日：2001-06-19

申请人： Byung-Gil Jeon ,  Ki-Nam Kim

发明人： Byung-Gil Jeon ,  Ki-Nam Kim

IPC分类号： G11C700

CPC分类号： G11C29/785 ,  G11C29/808

摘要： A redundancy circuit for a semiconductor memory device. The redundancy circuit includes redundancy memory cells and a redundancy word line decoder. The redundancy word line decoder has a fuse circuit that includes fuses and an output signal. The output signal is in one of three states depending on input signals. The fuse circuit controls a cutting of the fuses in accordance with the input signals so as to replace defective normal memory cells with the redundancy memory cells depending on a type of defect experienced by the defective normal memory cells.

公开(公告)号：US06388281B1

公开(公告)日：2002-05-14

申请号：US09617912

申请日：2000-07-17

申请人： Dong-Jin Jung ,  Ki-Nam Kim

发明人： Dong-Jin Jung ,  Ki-Nam Kim

IPC分类号： H01L2976

CPC分类号： H01L27/11502 ,  H01L21/31604 ,  H01L21/3162 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75

摘要： Disclosed is a triple metal line 1T/1C ferroelectric memory device and a method to make the same. A ferroelectric capacitor is connected to the transistor through a buried contact plug. An oxidation barrier layer lies between the contact plug and the lower electrode of the capacitor. A diffusion barrier layer covers the ferroelectric capacitor to prevent diffusion of material into or out of capacitor. As a result of forming the oxidation barrier layer, the contact plug is not exposed to the ambient oxygen atmosphere thereby providing a reliable ohmic contact between the contact plug and the lower electrode. Also, the memory device provides a triple interconnection structure made of metal, which improves device operation characteristics.

摘要翻译： 公开了三金属线1T / 1C铁电存储器件及其制造方法。 铁电电容器通过埋入式接触插头连接到晶体管。 氧化阻挡层位于电容器的接触插塞和下电极之间。 扩散阻挡层覆盖铁电电容器以防止材料扩散进入或流出电容器。 作为形成氧化阻挡层的结果，接触塞不暴露于环境氧气氛中，从而在接触塞和下电极之间提供可靠的欧姆接触。 此外，存储器件提供由金属制成的三重互连结构，这提高了器件操作特性。

公开(公告)号：US06262446B1

公开(公告)日：2001-07-17

申请号：US09369991

申请日：1999-08-06

申请人： Bon-Jae Koo ,  Ki-Nam Kim

发明人： Bon-Jae Koo ,  Ki-Nam Kim

IPC分类号： H01L27108

CPC分类号： H01L27/10844 ,  H01L21/76838 ,  H01L27/10852 ,  H01L28/55 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66234 ,  H01L29/732 ,  H01L2924/0002 ,  H01L2924/00

摘要： Conductive plugs are formed in a first insulating layer on an integrated circuit substrate. A first conductive layer, a capacitor dielectric film and a second conductive layer are formed on the first insulating layer including on the conductive plugs. The second conductive layer, the capacitor dielectric film and the first conductive layer are patterned to define capacitors, each including a portion of the first conductive layer, a portion of the capacitor dielectric film thereon and a portion of the second conductive layer thereon, and to define a plurality of first conductive layer patterns that are free of the capacitor dielectric film and the second conductive layer thereon. At least a first of the capacitors is electrically connected to a conductive plug and at least a second of the capacitors is not electrically connected to a conductive plug. A second insulating layer is formed on the first insulating layer, on the capacitors and on the first conductive patterns. The second insulating layer includes therein first contact holes that selectively expose the first conductive layer patterns. A first level interconnection is formed in the first contact holes and on the second insulating layer to electrically contact the first conductive patterns and to selectively electrically interconnect selected ones of the first conductive patterns to one another on the second insulating layer. A third insulating layer is formed on the second insulating layer and on the first level interconnection. The third insulating layer includes therein second contact holes that selectively expose the first level interconnection and selected ones of the capacitors. A second level interconnection is formed in the second contact holes and on the third insulating layer to selectively electrically interconnect the at least one of the first capacitors, to selectively electrically contact the first level interconnection and to selectively electrically interconnect selective ones of the at least a second of the capacitors to one another and to the first level interconnection.

公开(公告)号：US06172386B2

公开(公告)日：2001-01-09

申请号：US09335699

申请日：1999-06-18

申请人： Dong-Jin Jung ,  Ki-Nam Kim

发明人： Dong-Jin Jung ,  Ki-Nam Kim

IPC分类号： H01L2976

CPC分类号： H01L27/11502 ,  H01L28/55

摘要： A ferroelectric capacitor with a ferroelectric film having a relatively larger amount of titanium constituent than zinconate constituent improves ferroelectric characteristics. The method for fabricating the ferroelectric capacitor includes the step of performing a heat treatment in an oxygen atmosphere after forming a contact opening in an insulating layer which covers an already formed ferroelectric capacitor. This heat treatment in an oxygen atmosphere can minimize undesirable side effects resulting from a platinum electrode oxidizing the ferroelectric film components.

摘要翻译： 具有比锌矿物成分更大量的钛铁氧体膜的铁电体电解质提高铁电特性。 制造铁电电容器的方法包括在覆盖已经形成的铁电电容器的绝缘层中形成接触开口之后在氧气氛中进行热处理的步骤。 在氧气氛中的这种热处理可以使由铂电极氧化铁电体膜组分导致的不期望的副作用最小化。

公开(公告)号：US08927755B2

公开(公告)日：2015-01-06

申请号：US14003276

申请日：2012-02-22

申请人： Min-Keun Oh ,  Ki-Nam Kim ,  Ki-Hyeong Seo ,  Dae-Gil Kwon

发明人： Min-Keun Oh ,  Ki-Nam Kim ,  Ki-Hyeong Seo ,  Dae-Gil Kwon

IPC分类号： C07F9/09

CPC分类号： C07F9/091

摘要： The present invention relates to I- and II-type crystals of L-α-glyceryl phosphoryl choline, and to a method for preparing same. More particularly, the present invention relates to noble I- and II-type anhydride crystals of L-α-glyceryl phosphoryl choline, which have a higher purity than conventional liquid L-α-glyceryl phosphoryl choline, and one advantage of which is that formulations and dosages of pharmaceuticals are easily modified, and another advantage of which is that the hygroscopicity of the crystals are much lower than that of conventional polymorphic crystals, providing excellent stability during storage. The present invention also relates to a method for preparing the I- and II-type crystals of L-α-glyceryl phosphoryl choline.

摘要翻译： 本发明涉及L-α-甘油磷酰胆碱的I型和II型晶体及其制备方法。 更具体地，本发明涉及具有比常规液体L-α-甘油磷酰胆碱更高纯度的L-α-甘油基磷酰胆碱的高级I型和II型酸酐晶体，其优点之一是制剂 并且药物的剂量容易改性，其另一个优点是结晶的吸湿性远低于常规多晶型晶体的吸湿性，在储存期间提供极好的稳定性。 本发明还涉及制备L-α-甘油磷酰胆碱的I型和II型晶体的方法。

公开(公告)号：US08324045B2

公开(公告)日：2012-12-04

申请号：US13137420

申请日：2011-08-15

申请人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

发明人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

IPC分类号： H01L21/8239 ,  H01L45/00

CPC分类号： H01L27/24 ,  Y10S977/774

摘要： A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate.

摘要翻译： 提供半导体器件及其形成方法。 该方法包括制备半导体衬底。 可以在半导体衬底上依次形成绝缘层。 可以在绝缘层之间形成有源元件。 可以在绝缘层中形成公共节点以电连接到有源元件。 公共节点和有源元件可以二维重复地布置在半导体衬底上。