公开(公告)号：US20110117713A1

公开(公告)日：2011-05-19

申请号：US12979890

申请日：2010-12-28

申请人： Jin-Taek Park ,  Young-Woo Park ,  Jang-Hyun You ,  Jung-Dal Choi

发明人： Jin-Taek Park ,  Young-Woo Park ,  Jang-Hyun You ,  Jung-Dal Choi

IPC分类号： H01L21/336 ,  H01L21/762

CPC分类号： H01L27/11573 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11592 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel barrier layer may comprise a part of the gate dielectric of the HVTs. The tunnel barrier layer may constitute the entire gate dielectric of the HVTs. The corresponding tunnel barrier layer may be formed between or upon shallow trench isolation (STIs). Therefore, the manufacturing efficiency of a driver chip IC may be increased.

摘要翻译： 集成电路包括闪存单元，以及包括低压晶体管（LVT）和高压晶体管（HVT））的外围电路。 集成电路包括包含SiON，SiN或其它高k材料的隧道势垒层。 隧道势垒层可以包括HVT的栅极电介质的一部分。 隧道势垒层可以构成HVT的整个栅电介质。 相应的隧道势垒层可以形成在浅沟槽隔离（STI）之间或之间。 因此，可以提高驱动器芯片IC的制造效率。

公开(公告)号：US20110095377A1

公开(公告)日：2011-04-28

申请号：US12984860

申请日：2011-01-05

申请人： Jong-Sun Sel ,  Jung-Dal Choi ,  Choong-Ho Lee ,  Ju-Hyuck Chung ,  Hee-Soo Kang ,  Dong-uk Choi

发明人： Jong-Sun Sel ,  Jung-Dal Choi ,  Choong-Ho Lee ,  Ju-Hyuck Chung ,  Hee-Soo Kang ,  Dong-uk Choi

IPC分类号： H01L27/088

CPC分类号： H01L23/485 ,  H01L21/76804 ,  H01L21/76816 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

摘要： In some embodiments, a semiconductor memory device includes a substrate that includes a cell array region and a peripheral circuit region. The semiconductor memory device further includes a device isolation pattern on the substrate. The device isolation pattern defines a first active region and a second active region within the cell array region and a third active region in the peripheral circuit region. The semiconductor memory device further includes a first common source region, a plurality of first source/drain regions, and a first drain region in the first active region. The semiconductor memory device further includes a second common source region, a plurality of second source/drain regions, and a second drain region in the second active region. The semiconductor memory device further includes a third source/drain region in the third active region. The semiconductor memory device further includes a common source line contacting the first and second common source regions.

摘要翻译： 在一些实施例中，半导体存储器件包括包括单元阵列区域和外围电路区域的衬底。 半导体存储器件还包括在衬底上的器件隔离图案。 器件隔离图案限定了单元阵列区域内的第一有源区和第二有源区以及外围电路区中的第三有源区。 半导体存储器件还包括第一有源区中的第一公共源极区，多个第一源极/漏极区和第一漏极区。 半导体存储器件还包括第二公共源极区域，多个第二源极/漏极区域和第二有源区域中的第二漏极区域。 半导体存储器件还包括第三有源区中的第三源/漏区。 半导体存储器件还包括与第一和第二公共源极区域接触的公共源极线。

公开(公告)号：US07893484B2

公开(公告)日：2011-02-22

申请号：US11683383

申请日：2007-03-07

申请人： Young-Woo Park ,  Jung-Dal Choi ,  Jae-Sung Sim

发明人： Young-Woo Park ,  Jung-Dal Choi ,  Jae-Sung Sim

IPC分类号： H01L29/792

CPC分类号： H01L27/11568

摘要： A semiconductor device (e.g., a non-volatile memory device) with improved data retention characteristics includes active regions that protrude above a top surface of a device isolation region. A tunneling insulating layer is formed on the active regions. Charge storage patterns (e.g., charge trap patterns) are formed so as to be spaced apart from each other. A blocking insulating layer and a gate are formed on the charge storage patterns.

摘要翻译： 具有改进的数据保留特性的半导体器件（例如，非易失性存储器件）包括突出在器件隔离区的顶表面上方的有源区。 在有源区上形成隧道绝缘层。 电荷存储模式（例如，电荷陷阱图案）被形成为彼此间隔开。 在电荷存储图案上形成阻挡绝缘层和栅极。

公开(公告)号：US20100271873A1

公开(公告)日：2010-10-28

申请号：US12830464

申请日：2010-07-06

申请人： Ki-Tae Park ,  Jung-Dal Choi ,  Sung-Kyu Jo

发明人： Ki-Tae Park ,  Jung-Dal Choi ,  Sung-Kyu Jo

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/24

摘要： A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.

摘要翻译： 用于非易失性半导体存储器件的页面缓冲器包括被配置为将耦合到第一存储器单元的第一位线耦合到耦合到第二存储器单元的第二位线的开关，耦合到第一位线并被配置为传送的第一锁存块 向第一存储器单元提供第一锁存数据，以及耦合到第二位线和第一锁存块的第二锁存块，并且被配置为将第二锁存数据传送到第二存储器单元。

公开(公告)号：US07821825B2

公开(公告)日：2010-10-26

申请号：US12358009

申请日：2009-01-22

申请人： Ki-Tae Park ,  Jung-Dal Choi

发明人： Ki-Tae Park ,  Jung-Dal Choi

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A method of programming a flash memory includes applying a shielding voltage to at least one shielding line, which is interposed between a plurality of wordlines and a selection line and operable to reduce capacitance-coupling between the wordline and the selection line during the programming operation, and applying a program voltage to memory cells through one of the wordlines.

摘要翻译： 一种对闪速存储器进行编程的方法包括：对至少一个屏蔽线施加屏蔽电压，该屏蔽线介于多个字线和选择线之间，并且可操作以在编程操作期间减小字线和选择线之间的电容耦合， 以及通过字线之一向存储器单元施加编程电压。

公开(公告)号：US07812390B2

公开(公告)日：2010-10-12

申请号：US11777293

申请日：2007-07-13

申请人： Ki-Tae Park ,  Jung-Dal Choi ,  Jae-Sung Sim

发明人： Ki-Tae Park ,  Jung-Dal Choi ,  Jae-Sung Sim

IPC分类号： H01L25/065 ,  H01L27/115

CPC分类号： H01L27/11551 ,  G11C11/5621 ,  G11C16/0483 ,  G11C2211/5641 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device includes a first substrate having at least one string including a first select transistor, a second select transistor, and first memory cells connected in series between the first and second select transistors of the first substrate. The semiconductor memory device further includes a second substrate having at least one string including a first select transistor, a second select transistor, and second memory cells connected in series between the first and second select transistors of the second substrate. The number of the first memory cells of the at least one string of the first substrate is different from a number of the second memory cells of the at least one string of the second substrate. For example, the number of second memory cells may be less than the number of first memory cells.

摘要翻译： 半导体存储器件包括具有包括第一选择晶体管，第二选择晶体管和串联连接在第一衬底的第一和第二选择晶体管之间的第一存储单元的至少一个串的第一衬底。 半导体存储器件还包括具有至少一个串的第二衬底，该至少一个串包括串联连接在第二衬底的第一和第二选择晶体管之间的第一选择晶体管，第二选择晶体管和第二存储单元。 第一衬底的至少一个串的第一存储器单元的数量与第二衬底的至少一个串的第二存储单元的数量不同。 例如，第二存储器单元的数量可以小于第一存储器单元的数量。

公开(公告)号：US07776687B2

公开(公告)日：2010-08-17

申请号：US11797401

申请日：2007-05-03

申请人： Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Ju-Hyung Kim ,  Sang-Hun Jeon

发明人： Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Ju-Hyung Kim ,  Sang-Hun Jeon

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/823462 ,  H01L21/823475 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/7883

摘要： A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer through the opening.

摘要翻译： 半导体器件具有栅极接触结构，包括半导体衬底，用作晶体管的栅电极的多晶硅层，中间导电层，具有暴露多晶硅层的开口的顶部金属层和直接接触的接触插塞 使多晶硅层通过开口接触。

公开(公告)号：US07773422B2

公开(公告)日：2010-08-10

申请号：US12052666

申请日：2008-03-20

申请人： Ki-Tae Park ,  Jung-Dal Choi ,  Sung-Kyu Jo

发明人： Ki-Tae Park ,  Jung-Dal Choi ,  Sung-Kyu Jo

IPC分类号： G11C11/04

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/24

摘要： A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.

摘要翻译： 用于非易失性半导体存储器件的页面缓冲器包括被配置为将耦合到第一存储器单元的第一位线耦合到耦合到第二存储器单元的第二位线的开关，耦合到第一位线并被配置为传送的第一锁存块 向第一存储器单元提供第一锁存数据，以及耦合到第二位线和第一锁存块的第二锁存块，并且被配置为将第二锁存数据传送到第二存储器单元。

公开(公告)号：US07772639B2

公开(公告)日：2010-08-10

申请号：US11700315

申请日：2007-01-31

申请人： Chang-Seok Kang ,  Jung-Dal Choi ,  Ju-Hyung Kim ,  Jong-Sun Sel ,  Jae-Sung Sim ,  Sang-Hun Jeon

发明人： Chang-Seok Kang ,  Jung-Dal Choi ,  Ju-Hyung Kim ,  Jong-Sun Sel ,  Jae-Sung Sim ,  Sang-Hun Jeon

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： Nonvolatile memory devices including device isolation patterns on a semiconductor substrate are provided. The device isolation patterns define a cell active region and a peripheral active region of the semiconductor substrate. Cell gate electrodes are provided that cross over the cell active regions. Memory cell patterns are provided between the cell gate electrodes and the cell active regions and extend toward the device isolation patterns. A tunnel insulation film is provided between the memory cell pattern and the cell active region. Related methods of fabricating nonvolatile memory devices are also provided herein.

摘要翻译： 提供包括半导体衬底上的器件隔离图案的非易失性存储器件。 器件隔离图案限定半导体衬底的单元有源区和外围有源区。 提供跨越电池有源区的电池栅电极。 在单元栅极电极和单元有源区之间提供存储单元图案，并朝向器件隔离图案延伸。 在存储单元图形和单元有源区之间设置隧道绝缘膜。 本文还提供了制造非易失性存储器件的相关方法。

公开(公告)号：US07759723B2

公开(公告)日：2010-07-20

申请号：US12133858

申请日：2008-06-05

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byoung-Woo Ye

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byoung-Woo Ye

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/792

摘要： A non-volatile memory device includes a tunneling insulating layer on a semiconductor substrate, a charge storage layer, a blocking insulating layer, and a gate electrode. The charge storage layer is on the tunnel insulating layer and has a smaller band gap than the tunnel insulating layer and has a greater band gap than the semiconductor substrate. The blocking insulating layer is on the charge storage layer and has a greater band gap than the charge storage layer and has a smaller band gap than the tunnel insulating layer. The gate electrode is on the blocking insulating layer.