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公开(公告)号：US11024379B2
公开(公告)日：2021-06-01
申请号：US16667773
申请日：2019-10-29
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Amit Sharma , John Paul Strachan , Suhas Kumar , Catherine Graves , Martin Foltin , Craig Warner
Abstract: Systems and methods for providing write process optimization for memristors are described. Write process optimization circuitry manipulates the memristor's write operation, allowing the number of cycles in the write process is reduced. Write process optimization circuitry can include write current integration circuitry that measures an integral of a write current over time. The write optimization circuitry can also include shaping circuitry. The shaping circuitry can shape a write pulse, by determining the pulse's termination, width, and slope. The write pulse is shaped depending upon whether the target memristor device exhibits characteristics of “maladroit” cells or “adroit” cells. The pulse shaping circuitry uses the integral and measured write current to terminate the write pulse in a manner that allows the memristor, wherein having maladroit cells and adroit cells, to reach a target state. Thus, utility of memristors is enhanced by realizing an optimized write process with decrease latency and improved efficiency.
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公开(公告)号：US10930348B1
公开(公告)日：2021-02-23
申请号：US16539868
申请日：2019-08-13
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Can Li , Catherine Graves , John Paul Strachan
IPC: G11C15/00 , G11C15/04 , G11C11/408 , G11C11/413 , G11C8/12
Abstract: A reprogrammable dot product engine ternary content addressable memory (DPE-TCAM) is provided. The DPE-TCAM comprises a TCAM crossbar array comprising a plurality of match lines and a plurality of search lines. Each search line and match line are coupled together by a memory cell. A plurality of search line drivers are configured to apply a voltage signal to the search lines representing bits of a search word. Current sensing circuitry is coupled to the output of the plurality of match lines and configured to sense a current on the match lines, the sensed current indicating whether the search word and a stored word matched and, if not, the degree of mismatch between the two words.
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公开(公告)号：US20210049125A1
公开(公告)日：2021-02-18
申请号：US17072918
申请日：2020-10-16
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Dejan S. Milojicic , Kirk M. Bresniker , Paolo Faraboschi , John Paul Strachan
Abstract: A method of computing in memory, the method including inputting a packet including data into a computing memory unit having a control unit, loading the data into at least one computing in memory micro-unit, processing the data in the computing in memory micro-unit, and outputting the processed data. Also, a computing in memory system including a computing in memory unit having a control unit, wherein the computing in memory unit is configured to receive a packet having data and a computing in memory micro-unit disposed in the computing in memory unit, the computing in memory micro-unit having at least one of a memory matrix and a logic elements matrix.
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公开(公告)号：US20210021620A1
公开(公告)日：2021-01-21
申请号：US17042778
申请日：2018-04-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Catherine Graves , John Paul Strachan
IPC: H04L29/06
Abstract: A secondary ternary content-addressable memory (TCAM) is programmed with a new regular expression to be added to a regular expression pattern set. Incoming data strings are processed against a primary TCAM programmed with the regular expression pattern set and against the secondary TCAM in parallel.
While the incoming data strings are processed against the primary TCAM and against the secondary TCAM in parallel, the regular expression pattern set is updated to add the new regular expression.-
公开(公告)号：US20200312406A1
公开(公告)日：2020-10-01
申请号：US16364717
申请日：2019-03-26
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Amit S. Sharma , John Paul Strachan , Catherine Graves , Suhas Kumar , Craig Warner , Martin Foltin
Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.
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Patent Agency Ranking
公开(公告)号：US20200097440A1
公开(公告)日：2020-03-26
申请号：US16139913
申请日：2018-09-24
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Dejan S. Milojicic , Kirk M. Bresniker , Paolo Faraboschi , John Paul Strachan
Abstract: A method of computing in memory, the method including inputting a packet including data into a computing memory unit having a control unit, loading the data into at least one computing in memory micro-unit, processing the data in the computing in memory micro-unit, and outputting the processed data. Also, a computing in memory system including a computing in memory unit having a control unit, wherein the computing in memory unit is configured to receive a packet having data and a computing in memory micro-unit disposed in the computing in memory unit, the computing in memory micro-unit having at least one of a memory matrix and a logic elements matrix.
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公开(公告)号：US10482940B2
公开(公告)日：2019-11-19
申请号：US16062578
申请日：2015-12-17
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Miao Hu , John Paul Strachan , Zhiyong Li , Stanley Williams
Abstract: Example implementations of the present disclosure relate to improved computational accuracy in a crossbar array. An example system may include a crossbar array, having a plurality of memory elements at junctions, usable in performance of computations. The example system may further include a calculate engine to calculate ideal conductance of memory elements at a plurality of junctions of the crossbar array and a determine engine to determine conductance of the memory elements at the plurality of junctions of the crossbar array. An adjust engine of the example system may be used to adjust conductance of at least one memory element to improve computational accuracy by reduction of a difference between the ideal conductance and the determined conductance of the at least one memory element.
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公开(公告)号：US20190332708A1
公开(公告)日：2019-10-31
申请号：US15966817
申请日：2018-04-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： John Paul Strachan , Catherine Graves
Abstract: Filters are represented as k-SAT solutions. A filter query includes a k-SAT clause having literals pertaining to variables. A ternary content-addressable memory (TCAM) has cells programmed in correspondence with the k-SAT solutions. Input column lines of the TCAM that correspond to variables to which the literals of the k-SAT clause pertain are set in accordance with inversions of the literals. Input column lines of the TCAM that correspond to variables to which no literal of the k-SAT clause pertains are set in accordance with a “don't care” state. Responsive to any output match row line of the TCAM being set, the filter query is indicated as failing to satisfy the filters. Responsive to no output match row line of the TCAM being set, the filter query is indicated as satisfying the filters.
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公开(公告)号：US20190235458A1
公开(公告)日：2019-08-01
申请号：US16354076
申请日：2019-03-14
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Brent Buchanan , John Paul Strachan , Le Zheng
IPC: G05B19/045 , G11C15/04
CPC classification number: G05B19/045 , G05B2219/23289 , G11C7/1006 , G11C15/04
Abstract: An example finite state machine may include a content-addressable memory. The content-addressable memory may include blocks that respectively store input-terms of the finite state machine. The finite state machine may be configured to, for each received input: select a subset of the blocks of the content addressable memory to enable for searching, the subset being selected based on a current state of the finite state machine, and determine a next state of the finite state machine by searching the currently enabled subset of blocks of the content addressable memory based on the input.
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公开(公告)号：US20190114141A1
公开(公告)日：2019-04-18
申请号：US16218636
申请日：2018-12-13
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Brent Buchanan , Le Zheng , John Paul Strachan
Abstract: In some examples, a method may be performed by a multiply-accumulate circuit. As part of the method a row driver of the multiply-accumulate circuit may drive a row value line based on an input vector bit of an input vector received by the row driver. The row driver may also drive a row line that controls a corresponding memristor according to the input vector bit. The corresponding memristor may store a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation. The method may further include a sense amplifier generating an output voltage based on a current output from the corresponding memristor and counter circuitry adjusting a counter value that represents a running total of the multiply-accumulate operation based on the row value line, the output voltage generated by the sense amplifier, or a combination of both.
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