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    Method for Intermittently Producing 4,4'-Diaminodicyclohexylmethane with a Low Amount of the Trans-trans Isomer
    62.
    发明申请
    Method for Intermittently Producing 4,4'-Diaminodicyclohexylmethane with a Low Amount of the Trans-trans Isomer 有权
    间歇生产低反式异构体的4,4'-二氨基二环己基甲烷的方法

    公开(公告)号：US20120323041A1

    公开(公告)日：2012-12-20

    申请号：US13517195

    申请日：2011-06-03

    申请人： Shuang Hu ,  Hao Chen ,  Zilin Ni ,  Wangshun Qi ,  Zhongying Chen ,  Zhiyuan Liu ,  Xudong Wang ,  Zhanyu Zhao ,  Weiqi Hua

    发明人： Shuang Hu ,  Hao Chen ,  Zilin Ni ,  Wangshun Qi ,  Zhongying Chen ,  Zhiyuan Liu ,  Xudong Wang ,  Zhanyu Zhao ,  Weiqi Hua

    IPC分类号： C07C209/00

    CPC分类号： C07C209/72 ,  C07C209/86 ,  C07C2601/14 ,  C07C211/36

    摘要： The present invention discloses a method for intermittently producing 4,4′-diaminodicyclohexyl methane (H12MDA) with a low amount of the trans-trans isomer thereof, which comprises: controlling the reaction process by stopping the reaction when, except for a solvent, the reaction solution comprises MDA of 0-5 wt % and H6MDA of 1-20 wt %; and b) separating the reaction solution obtained from step a) by conventional means to obtain H12MDA product with desired purity, and allowing the un-reacted material and intermediate product to be recycled to the reactor after being accumulated. The method of the present invention decreases the amount of the trans-trans isomer in H12MDA, increases the yield of the reaction, and reduces the production cost. The present invention also provides a post treatment process of the reaction mixture.

    摘要翻译： 本发明公开了间歇地制备低反式异构体的4,4'-二氨基二环己基甲烷（H12MDA）的方法，该方法包括：除溶剂外，通过停止反应来控制反应过程 反应溶液包含0-5重量％的MDA和1-20重量％的H6MDA; 和b）通过常规方法分离由步骤a）获得的反应溶液以获得具有所需纯度的H12MDA产物，并且使未反应的材料和中间产物在积聚后再循环到反应器中。 本发明的方法降低了H12MDA中反式异构体的量，提高了反应的产率，降低了生产成本。 本发明还提供了反应混合物的后处理方法。

    Memory controller with loopback test interface
    63.
    发明授权
    Memory controller with loopback test interface 有权
    带环回测试接口的内存控制器

    公开(公告)号：US08301941B2

    公开(公告)日：2012-10-30

    申请号：US13305202

    申请日：2011-11-28

    申请人： Luka Bodrozic ,  Sukalpa Biswas ,  Hao Chen ,  Sridhar P. Subramanian ,  James B. Keller

    发明人： Luka Bodrozic ,  Sukalpa Biswas ,  Hao Chen ,  Sridhar P. Subramanian ,  James B. Keller

    IPC分类号： G01R31/28 ,  G11C29/00 ,  G06F11/00

    CPC分类号： G01R31/31716

    摘要： An apparatus may include an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller may be programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller may be configured to receive a first write operation from the processor over the interconnect. The memory controller may be configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller may be further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.

    摘要翻译： 设备可以包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。 存储器控制器可以由处理器编程成环回测试操作模式，并且在回送测试模式中，存储器控制器可以被配置为通过互连从处理器接收第一写入操作。 存储器控制器可以被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。 存储器控制器还可以被配置为在互连上将读数据作为读数据返回，用于从互连上的处理器接收到的第一读操作。

    System for Automatically Adjusting Sound Effects and Method Thereof
    65.
    发明申请
    System for Automatically Adjusting Sound Effects and Method Thereof 审中-公开
    自动调节声音效果及方法的系统

    公开(公告)号：US20120186418A1

    公开(公告)日：2012-07-26

    申请号：US13359161

    申请日：2012-01-26

    申请人： Hao Chen ,  Yun-Fei Wei

    发明人： Hao Chen ,  Yun-Fei Wei

    IPC分类号： G10H1/02

    CPC分类号： G10H1/0091 ,  G10H1/46 ,  G10H2240/145

    摘要： A system for automatically adjusting sound effects and a method thereof. The system includes a communication module, a playing module, an input module for receiving a choice among a plurality of songs made by a user, and a processing module configured to search a storage module for one of sets of sound effects parameters corresponding to the choice made by the user. If the set of sound effects parameters corresponding to the choice made by the user is not found, the processing module is then configured to obtain the set of sound effects parameters from a plurality of servers through a communication module. The playing module is configured to adjust a playing mode according to the set of sound effects parameters found or obtained by the processing module, and to play the song of choice in the playing mode.

    摘要翻译： 一种用于自动调节声音效果的系统及其方法。 该系统包括通信模块，播放模块，用于接收由用户制作的多首歌曲中的选择的输入模块以及配置成搜索存储模块中与选择对应的一组声音效果参数之一的处理模块 由用户制作 如果没有找到与用户做出的选择相对应的一组声音效果参数，则处理模块然后被配置为通过通信模块从多个服务器获得一组声音效果参数。 播放模块被配置为根据由处理模块找到或获得的声音效果参数的集合来调整播放模式，并且在播放模式下播放所选择的歌曲。

    Mechanism for an Efficient DLL Training Protocol During a Frequency Change
    66.
    发明申请
    Mechanism for an Efficient DLL Training Protocol During a Frequency Change 有权
    频率变化期间高效率的DLL训练协议的机制

    公开(公告)号：US20120126868A1

    公开(公告)日：2012-05-24

    申请号：US12951788

    申请日：2010-11-22

    申请人： Erik P. Machnicki ,  Hao Chen ,  Sanjay Mansingh

    发明人： Erik P. Machnicki ,  Hao Chen ,  Sanjay Mansingh

    IPC分类号： H03L7/06

    CPC分类号： H03L7/07 ,  H03L7/0814

    摘要： An efficient delay locked loop (DLL) training protocol during a frequency change includes an integrated circuit with a memory physical layer (PHY) unit that includes a master DLL and a slave DLL. The master DLL may delay a first reference clock by an amount, and provide a reference delay value corresponding to the delay amount. The slave DLL may delay a second reference clock by a second amount based upon a received configuration delay value. An interface unit may generate the configuration delay value based upon the reference delay value. A power management unit may provide an indication that the frequency of the second reference clock is changing. In response to receiving the indication, the interface unit may generate a new configuration delay value that corresponds to the new frequency using a predetermined scaling value and provide the new configuration delay value to the memory PHY unit.

    摘要翻译： 在频率变化期间，有效的延迟锁定环（DLL）训练协议包括具有包含主DLL和从属DLL的存储器物理层（PHY）单元的集成电路。 主DLL可以将第一参考时钟延迟一定量，并提供对应于延迟量的参考延迟值。 从属DLL可以基于接收的配置延迟值将第二参考时钟延迟第二量。 接口单元可以基于参考延迟值生成配置延迟值。 功率管理单元可以提供第二参考时钟的频率正在改变的指示。 响应于接收到指示，接口单元可以使用预定的缩放值来生成对应于新频率的新的配置延迟值，并向存储器PHY单元提供新的配置延迟值。

    Memory Controller with Loopback Test Interface
    67.
    发明申请
    Memory Controller with Loopback Test Interface 有权
    带环回测试接口的内存控制器

    公开(公告)号：US20120072787A1

    公开(公告)日：2012-03-22

    申请号：US13305202

    申请日：2011-11-28

    申请人： Luka Bodrozic ,  Sukalpa Biswas ,  Hao Chen ,  Sridhar P. Subramanian ,  James B. Keller

    发明人： Luka Bodrozic ,  Sukalpa Biswas ,  Hao Chen ,  Sridhar P. Subramanian ,  James B. Keller

    IPC分类号： G01R31/28 ,  G06F11/26

    CPC分类号： G01R31/31716

    摘要： In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.

    摘要翻译： 在一个实施例中，一种装置包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。 存储器控制器可由处理器编程为环回测试操作模式，并且在环回测试模式中，存储器控制器被配置为通过互连从处理器接收第一写入操作。 存储器控制器被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。 所述存储器控制器还被配置为将所述写入数据作为所述互连上的读取数据返回，用于从所述互连处从所述处理器接收的第一读取操作。

    Multi-Ported Memory Controller with Ports Associated with Traffic Classes
    68.
    发明申请
    Multi-Ported Memory Controller with Ports Associated with Traffic Classes 审中-公开
    具有与流量类相关的端口的多端口存储器控制器

    公开(公告)号：US20120072677A1

    公开(公告)日：2012-03-22

    申请号：US12883848

    申请日：2010-09-16

    申请人： Sukalpa Biswas ,  Hao Chen

    发明人： Sukalpa Biswas ,  Hao Chen

    IPC分类号： G06F12/00

    CPC分类号： G06F13/18

    摘要： In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

    摘要翻译： 在一个实施例中，存储器控制器包括多个端口。 每个端口可能专用于不同类型的流量。 在一个实施例中，可以为业务类型定义服务质量（QoS）参数，并且不同的业务类型可以具有不同的QoS参数定义。 存储器控制器可以被配置为基于QoS参数在不同端口上接收的调度操作。 在一个实施例中，当接收到具有较高QoS参数，经由边带请求和/或通过操作老化的后续操作时，存储器控制器可以支持QoS参数的升级。 在一个实施例中，存储器控制器被配置为当操作流过存储器控制器管线时，减少对QoS参数的强调并且增加对存储器带宽优化的重视。

    PORTABLE DATA CARRIER COMPRISING A CAT INTERPRETER
    70.
    发明申请
    PORTABLE DATA CARRIER COMPRISING A CAT INTERPRETER 有权
    包含CAT解码器的便携式数据载体

    公开(公告)号：US20110111802A1

    公开(公告)日：2011-05-12

    申请号：US12812822

    申请日：2009-01-15

    申请人： Oliver Richter ,  Stephan Spitz ,  Hao Chen

    发明人： Oliver Richter ,  Stephan Spitz ,  Hao Chen

    IPC分类号： H04M1/00 ,  G06F17/00

    CPC分类号： H04W4/60 ,  H04L67/02 ,  H04W88/02

    摘要： The invention relates to a method on a portable data carrier (10). In said method, a web server (62) of the data carrier (10) preferably receives command information from a terminal (100) connected to the data carrier (10), the command information relating to at least one CAT command (“Card Application Toolkit” command). The at least one CAT command is then executed by a CAT interpreter (64) of the data carrier (10). The command information is embedded in an HTTP command request message of an HTTP client (110) of the terminal (100), and the web server (62) extracts the embedded command information from the HTTP command request message before relaying it to the CAT interpreter (64) of the data carrier (10) for execution of the at least one CAT command. In this manner there is enabled a flexible and resource-saving interaction between the web server (62) and the CAT interpreter (64).

    摘要翻译： 本发明涉及一种便携式数据载体（10）上的方法。 在所述方法中，数据载体（10）的网络服务器（62）优选地从连接到数据载体（10）的终端（100）接收命令信息，与至少一个CAT命令相关的命令信息 工具包“命令）。 然后由数据载体（10）的CAT解释器（64）执行至少一个CAT命令。 所述命令信息被嵌入到所述终端（100）的HTTP客户端（110）的HTTP命令请求消息中，并且所述Web服务器（62）在将其传递给所述CAT解释器之前从所述HTTP命令请求消息中提取所述嵌入的命令信息 （10）的数据载体（64），用于执行所述至少一个CAT命令。 以这种方式，可以在web服务器（62）和CAT解释器（64）之间实现灵活和资源节约的交互。