公开(公告)号：US11715693B2

公开(公告)日：2023-08-01

申请号：US16397923

申请日：2019-04-29

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Adel A. Elsherbini ,  Henning Braunisch ,  Johanna M. Swan ,  Telesphor Kamgaing

IPC: H01L23/538 ,  H01L23/66 ,  G02B6/30 ,  H01P3/16 ,  H01P11/00

CPC classification number: H01L23/538 ,  G02B6/30 ,  H01L23/66 ,  H01P3/16 ,  H01P11/006 ,  H01L2223/6627

Abstract: Embodiments may relate to a semiconductor package that includes a package substrate coupled with a die. The package may further include a waveguide coupled with the first package substrate. The waveguide may include two or more layers of a dielectric material with a waveguide channel positioned between two layers of the two or more layers of the dielectric material. The waveguide channel may convey an electromagnetic signal with a frequency greater than 30 gigahertz (GHz). Other embodiments may be described or claimed.

公开(公告)号：US11688660B2

公开(公告)日：2023-06-27

申请号：US16534820

申请日：2019-08-07

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Feras Eid ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H01Q23/00 ,  H01Q1/52 ,  H01Q1/02 ,  H01L23/36 ,  H01L23/538 ,  H01L23/552

CPC classification number: H01L23/36 ,  H01L23/5381 ,  H01L23/552

Abstract: Embodiments may relate to a radio frequency (RF) multi-chip module that includes a first RF die and a second RF die. The first and second RF dies may be coupled with a package substrate at an inactive side of the respective dies. A bridge may be coupled with an active side of the first and second RF dies die such that the first and second RF dies are communicatively coupled through the bridge, and such that the first and second RF dies are at least partially between the package substrate and the bridge. Other embodiments may be described or claimed.

公开(公告)号：US20230197675A1

公开(公告)日：2023-06-22

申请号：US17552845

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Gerald S. Pasdast ,  Yidnekachew Mekonnen ,  Adel A. Elsherbini ,  Peipei Wang ,  Vivek Kumar Rajan ,  Georgios Dogiamis

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/481 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/37001

Abstract: Embodiments of the present disclosure provide a microelectronic assembly comprising: a first integrated circuit (IC) die, the first IC die comprising an input/output (IO) circuit; and a plurality of IC dies, the plurality of IC dies comprising a second IC die, the second IC die comprising a microcontroller circuit to control the IO circuit, wherein the first IC die and the plurality of IC dies are coupled with interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects.

公开(公告)号：US20230163098A1

公开(公告)日：2023-05-25

申请号：US17531374

申请日：2021-11-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  William J. Lambert ,  Krishna Bharath ,  Shawna M. Liff ,  Nicolas Butzen ,  Georgios Dogiamis ,  Gerald S. Pasdast ,  Vivek Kumar Rajan ,  Sathya Narasimman Tiagaraj ,  Timothy Francis Schmidt

IPC: H01L25/065

CPC classification number: H01L25/0652 ,  H01L25/18

Abstract: Embodiments of the present disclosure provide a microelectronic assembly comprising: an integrated circuit (IC) die in a first layer and a plurality of IC dies in a second layer, at least two adjacent IC dies in the plurality being electrically coupled along their proximate edges by the IC die. The first layer and the second layer are electrically and mechanically coupled by interconnects having a pitch of less than 10 micrometers between adjacent interconnects, and the IC die comprises capacitors and voltage regulator circuitry.

公开(公告)号：US11652264B2

公开(公告)日：2023-05-16

申请号：US17582271

申请日：2022-01-24

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Adel A. Elsherbini

IPC: H01P1/208 ,  H01P3/12 ,  H01P11/00 ,  H01P5/10 ,  H01P1/20 ,  H01P7/06 ,  H01P1/213 ,  H01P5/12 ,  H01P5/16

CPC classification number: H01P1/2088 ,  H01P1/2002 ,  H01P1/2138 ,  H01P3/121 ,  H01P5/10 ,  H01P5/12 ,  H01P7/065 ,  H01P11/002 ,  H01P11/007 ,  H01P11/008 ,  H01P5/16

Abstract: Microelectronic assemblies that include a lithographically-defined substrate integrated waveguide (SIW) component, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate portion having a first face and an opposing second face; and an SIW component that may include a first conductive layer on the first face of the package substrate portion, a dielectric layer on the first conductive layer, a second conductive layer on the dielectric layer, and a first conductive sidewall and an opposing second conductive sidewall in the dielectric layer, wherein the first and second conductive sidewalls are continuous structures.

公开(公告)号：US11605603B2

公开(公告)日：2023-03-14

申请号：US16397718

申请日：2019-04-29

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Henning Braunisch ,  Johanna M. Swan ,  Shawna M. Liff ,  Aleksandar Aleksov

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/66

Abstract: Embodiments may relate to a microelectronic package that includes a radio frequency (RF) chip coupled with a die by interconnects with a first pitch. The RF chip may further be coupled with a waveguide of a package substrate by interconnects with a second pitch that is different than the first pitch. The RF chip may facilitate conveyance of data to the waveguide as an electromagnetic signal with a frequency greater than approximately 20 gigahertz (GHz). Other embodiments may be described or claimed.

公开(公告)号：US11581272B2

公开(公告)日：2023-02-14

申请号：US16394537

申请日：2019-04-25

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Adel A. Elsherbini ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Richard Dischler ,  Johanna M. Swan ,  Victor J. Prokoff

IPC: H01L23/66 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

Abstract: Embodiments may relate to a multi-chip microelectronic package that includes a first die and a second die coupled to a package substrate. The first and second dies may have respective radiative elements that are communicatively coupled with one another such that they may communicate via an electromagnetic signal with a frequency at or above approximately 20 gigahertz (GHz). Other embodiments may be described or claimed.

公开(公告)号：US11476554B2

公开(公告)日：2022-10-18

申请号：US16613386

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Sasha Oster ,  Telesphor Kamgaing ,  Erich Ewy ,  Adel Elsherbini ,  Johanna Swan

IPC: H01P3/16 ,  H01P5/02 ,  B60R16/023 ,  H01L23/66 ,  H01L25/18 ,  H01R13/622 ,  H01R13/631 ,  H01R13/646 ,  H05K1/18 ,  H05K5/00 ,  H05K5/02 ,  H05K7/20

Abstract: Embodiments of the invention include dielectric waveguides and connectors for dielectric waveguides. In an embodiment a dielectric waveguide connector may include an outer ring and one or more posts extending from the outer ring towards the center of the outer ring. In some embodiments, a first dielectric waveguide secured within the dielectric ring by the one or more posts. In another embodiment, an enclosure surrounding electronic components may include an enclosure wall having an interior surface and an exterior surface and a dielectric waveguide embedded within the enclosure wall. In an embodiment, a first end of the dielectric waveguide is substantially coplanar with the interior surface of the enclosure wall and a second end of the dielectric waveguide is substantially coplanar with the exterior surface of the enclosure wall.

公开(公告)号：US11437706B2

公开(公告)日：2022-09-06

申请号：US16369452

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Telesphor Kamgaing ,  Gilbert W. Dewey ,  Hyung-Jin Lee

IPC: H01L25/065 ,  H01Q1/22 ,  H01L23/00 ,  H01L23/66 ,  H01L23/552 ,  H01L25/00

Abstract: Embodiments may relate to an semiconductor package. The semiconductor package may include a die coupled with the face of the package substrate. The semiconductor package may further include a waveguide coupled with the face of the package substrate adjacent to the die, wherein the waveguide is to receive an electromagnetic signal from the die and facilitate conveyance of the electromagnetic signal in a direction parallel to the face of the package substrate. Other embodiments may be described or claimed.

公开(公告)号：US20220149500A1

公开(公告)日：2022-05-12

申请号：US17582271

申请日：2022-01-24

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Adel A. Elsherbini

IPC: H01P1/208 ,  H01P3/12 ,  H01P11/00 ,  H01P5/10 ,  H01P1/20 ,  H01P7/06

Abstract: Microelectronic assemblies that include a lithographically-defined substrate integrated waveguide (SIW) component, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate portion having a first face and an opposing second face; and an SIW component that may include a first conductive layer on the first face of the package substrate portion, a dielectric layer on the first conductive layer, a second conductive layer on the dielectric layer, and a first conductive sidewall and an opposing second conductive sidewall in the dielectric layer, wherein the first and second conductive sidewalls are continuous structures.