公开(公告)号：US11594270B2

公开(公告)日：2023-02-28

申请号：US16141827

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Sasikanth Manipatruni ,  Chia-Ching Lin ,  Dmitri Nikonov ,  Christopher Wiegand ,  Ian Young

IPC: G11C11/16 ,  G11C11/18 ,  H01L29/66

Abstract: An apparatus is provided which comprises: a magnetic junction having a magnet with perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device. In some embodiments, the apparatus comprises an interconnect partially adjacent to the structure of the magnetic junction, wherein the interconnect comprises a spin orbit material, wherein the interconnect has a pocket comprising non-spin orbit material, wherein the pocket is adjacent to the magnet of the magnetic junction. In some embodiments, the non-spin orbit material comprises metal which includes one or more of: Cu, Al, Ag, or Au.

公开(公告)号：US11574666B2

公开(公告)日：2023-02-07

申请号：US16246362

申请日：2019-01-11

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Sasikanth Manipatruni ,  Chia-Ching Lin ,  Kaan Oguz ,  Ian Young

IPC: G11C11/16 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L27/22

Abstract: A memory device includes a spin orbit electrode structure having a dielectric structure including a first sidewall, a second sidewall opposite to the first sidewall, a top surface. The spin orbit electrode structure further includes an electrode having a spin orbit material adjacent to the dielectric structure, where the electrode has a first electrode portion on the top surface, a second electrode portion adjacent to the first sidewall and a third electrode portion adjacent to the second sidewall. The first electrode portion, the second electrode portion and the third electrode portion are contiguous. The spin orbit electrode structure further includes a conductive interconnect in contact with the second electrode portion or the third electrode portion. The memory device further includes a magnetic junction device on a portion of the top surface of the first electrode portion.

公开(公告)号：US11557717B2

公开(公告)日：2023-01-17

申请号：US16193599

申请日：2018-11-16

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Tanay Gosavi ,  Sasikanth Manipatruni ,  Dmitri Nikonov ,  Ian Young

IPC: H01L43/02 ,  H01L27/22 ,  G11C11/16 ,  H01L43/10 ,  H01F10/32

Abstract: A memory apparatus is provided which comprises: a stack comprising a magnetic insulating material and a transition metal dichalcogenide (TMD), wherein the magnetic insulating material has a first magnetization. The stack behaves as a free magnet. The apparatus includes a fixed magnet with a second magnetization. An interconnect is further provided which comprises a spin orbit material, wherein the interconnect is adjacent to the stack.

公开(公告)号：US11476408B2

公开(公告)日：2022-10-18

申请号：US16144978

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Angeline Smith ,  Sasikanth Manipatruni ,  Christopher Wiegand ,  Tofizur Rahman ,  Noriyuki Sato ,  Benjamin Buford

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/08 ,  H01L27/22 ,  H01L43/10 ,  G11C11/16

Abstract: A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit coupling material and a perpendicular magnetic tunnel junction (pMTJ) device on a portion of the electrode. The pMTJ device includes a free magnet, a fixed magnet and a tunnel barrier layer in between, where at least one of the fixed magnet or the free magnet includes two magnetic layers and a spacer layer comprising tungsten in between.

公开(公告)号：US20220310147A1

公开(公告)日：2022-09-29

申请号：US17839345

申请日：2022-06-13

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sasikanth Manipatruni ,  Tanay Gosavi ,  Dmitri Nikonov ,  Benjamin Buford ,  Kaan Oguz ,  John J. Plombon ,  Ian A. Young

IPC: G11C11/16 ,  H01L43/02 ,  H01L43/10

Abstract: An apparatus is provided which comprises: a stack comprising a magnetic insulating material (MI such as EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene), wherein the magnetic insulating material has a first magnetization; a magnet with a second magnetization, wherein the magnet is adjacent to the TMD of the stack; and an interconnect comprising a spin orbit material, wherein the interconnect is adjacent to the magnet.

公开(公告)号：US11411172B2

公开(公告)日：2022-08-09

申请号：US16130912

申请日：2018-09-13

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Sasikanth Manipatruni ,  Daniel Morris ,  Kaushik Vaidyanathan ,  Tanay Karnik ,  Ian Young

IPC: G11C11/00 ,  H01L43/04 ,  H01L43/06 ,  G11C11/16 ,  G11C11/18 ,  H01L43/10

Abstract: An apparatus is provided which comprises a full adder including magnetoelectric material and spin orbit material. In some embodiments, the adder includes: a 3-bit carry generation structure and a multi-bit sum generation structure coupled to the 3-bit carry generation structure. In some embodiments, the 3-bit carry generation structure includes at least three cells comprising magnetoelectric material and spin orbit material, wherein the 3-bit carry generation structure is to perform a minority logic operation on first, second, and third inputs to generate a carry output. In some embodiments, the multi-bit sum generation structure includes at least four cells comprising magnetoelectric material and spin orbit material, wherein the multi-bit sum generation structure is to perform a minority logic operation on the first, second, and third inputs and the carry output to generate a sum output.

公开(公告)号：US11411046B2

公开(公告)日：2022-08-09

申请号：US16128278

申请日：2018-09-11

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Tanay Gosavi ,  Dmitri Nikonov ,  Ian Young

IPC: H01L27/16 ,  H01L37/00 ,  H01L25/16 ,  H01L35/32 ,  H01L35/30 ,  H01L29/417 ,  H01L29/06

Abstract: Electrical devices with an integral thermoelectric generator comprising a spin-Seebeck insulator and a spin orbit coupling material, and associated methods of fabrication. A spin-Seebeck thermoelectric material stack may be integrated into macroscale power cabling as well as nanoscale device structures. The resulting structures are to leverage the spin-Seebeck effect (SSE), in which magnons may transport heat from a source (an active device or passive interconnect) and through the spin-Seebeck insulator, which develops a resulting spin voltage. The SOC material is to further convert the spin voltage into an electric voltage to complete the thermoelectric generation process. The resulting electric voltage may then be coupled into an electric circuit.

公开(公告)号：US20220123206A1

公开(公告)日：2022-04-21

申请号：US17565106

申请日：2021-12-29

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sasikanth Manipatruni ,  Tanay Gosavi ,  Dmitri Nikonov ,  Benjamin Buford ,  Kaan Oguz ,  John J. Plombon ,  Ian A. Young

IPC: H01L43/10 ,  H01L43/02 ,  H01L27/22

Abstract: An apparatus is provided which comprises: a stack comprising a magnetoelectric (ME such as BiFeO3, (LaBi)FeO3, LuFeO3, PMN-PT, PZT, AlN, SmBiFeO3, Cr2O3, etc.) material and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, graphene, etc.); a magnet adjacent to a first portion of the TMD of the stack; a first interconnect adjacent to the magnet; a second interconnect adjacent to the ME material of the stack; and a third interconnect adjacent to a second portion of the TMD of the stack.

公开(公告)号：US11138499B2

公开(公告)日：2021-10-05

申请号：US16147176

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Jack T. Kavalieros ,  Ian A. Young ,  Sasikanth Manipatruni ,  Ram Krishnamurthy ,  Uygar Avci ,  Gregory K. Chen ,  Amrita Mathuriya ,  Raghavan Kumar ,  Phil Knag ,  Huseyin Ekin Sumbul ,  Nazila Haratipour ,  Van H. Le

IPC: G06N3/063 ,  H01L27/108 ,  H01L27/11502 ,  G06N3/04 ,  G06F17/16 ,  H01L27/11 ,  G11C11/54 ,  G11C7/10 ,  G11C11/419 ,  G11C11/409 ,  G11C11/22

Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

公开(公告)号：US11114144B2

公开(公告)日：2021-09-07

申请号：US16464260

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: G11C11/16 ,  H01L43/04 ,  H01L43/06 ,  H01L27/22 ,  H01L43/10 ,  H01L43/14

Abstract: An apparatus is provided which comprises: a first paramagnet; a stack of layers, a portion of which is adjacent to the first paramagnet, wherein the stack of layers is to provide an inverse Rashba-Edelstein effect; a second paramagnet; a magnetoelectric layer adjacent to the second paramagnet; and a conductor coupled to at least a portion of the stack of layers and the magnetoelectric layer.