公开(公告)号：US20220190159A1

公开(公告)日：2022-06-16

申请号：US17122907

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Rajat PAUL ,  Willy RACHMADY ,  Jessica TORRES ,  Rambert NAHM ,  Ashish AGRAWAL ,  Siddharth CHOUKSEY ,  Gilbert DEWEY ,  Jack T. KAVALIEROS

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L29/165 ,  H01L29/66 ,  H01L27/12

Abstract: Integrated circuit structures having GeSnB source or drain structures, and methods of fabricating integrated circuit structures having GeSnB source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include germanium, tin and boron.

公开(公告)号：US20220149209A1

公开(公告)日：2022-05-12

申请号：US17580550

申请日：2022-01-20

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Aaron LILAK ,  Van H. LE ,  Abhishek A. SHARMA ,  Tahir GHANI ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Nazila HARATIPOUR ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Seung Hoon SUNG ,  Shriram SHIVARAMAN

IPC: H01L29/786 ,  H01L29/66

Abstract: Thin film transistors having U-shaped features are described. In an example, integrated circuit structure including a gate electrode above a substrate, the gate electrode having a trench therein. A channel material layer is over the gate electrode and in the trench, the channel material layer conformal with the trench. A first source or drain contact is coupled to the channel material layer at a first end of the channel material layer outside of the trench. A second source or drain contact is coupled to the channel material layer at a second end of the channel material layer outside of the trench.

公开(公告)号：US20210407999A1

公开(公告)日：2021-12-30

申请号：US16913796

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Gilbert DEWEY ,  Anh PHAN ,  Nicole K. THOMAS ,  Urusa ALAAN ,  Seung Hoon SUNG ,  Christopher M. NEUMANN ,  Willy RACHMADY ,  Patrick MORROW ,  Hui Jae YOO ,  Richard E. SCHENKER ,  Marko RADOSAVLJEVIC ,  Jack T. KAVALIEROS ,  Ehren MANNEBACH

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/775 ,  H01L29/423

Abstract: Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.

公开(公告)号：US20210305388A1

公开(公告)日：2021-09-30

申请号：US16833184

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Rishabh MEHANDRU ,  Cory WEBER ,  Willy RACHMADY ,  Varun MISHRA

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/10 ,  H01L21/02

Abstract: Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin.

公开(公告)号：US20210296315A1

公开(公告)日：2021-09-23

申请号：US16827566

申请日：2020-03-23

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Rishabh MEHANDRU ,  Ehren MANNEBACH ,  Patrick MORROW ,  Willy RACHMADY

IPC: H01L27/092 ,  H01L29/10 ,  H01L23/498 ,  H01L23/528

Abstract: Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a first transistor strata. The first transistor strata comprises a first backbone, a first transistor adjacent to a first edge of the first backbone, and a second transistor adjacent to a second edge of the first backbone. In an embodiment, the semiconductor device further comprises a second transistor strata over the first transistor strata. The second transistor strata comprises a second backbone, a third transistor adjacent to a first edge of the second backbone, and a fourth transistor adjacent to a second edge of the second backbone.

公开(公告)号：US20210091080A1

公开(公告)日：2021-03-25

申请号：US16772636

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Ravi PILLARISETTY ,  Abhishek A. SHARMA ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG

IPC: H01L27/092 ,  H01L27/12 ,  H01L21/8254

Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS thin-film transistors (TFT).

公开(公告)号：US20200279941A1

公开(公告)日：2020-09-03

申请号：US16650834

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Willy RACHMADY ,  Gilbert DEWEY ,  Erica J. THOMPSON ,  Aaron D. LILAK ,  Jack T. KAVALIEROS

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165

Abstract: Disclosed are etchstop regions in fins of semiconductor devices, and related methods. A semiconductor device includes a buried region, a fin on the buried region, and a gate formed at least partially around the fin. At least a portion of the fin that borders the buried region includes an etchstop material. The etchstop material includes a doped semiconductor material that has a slower etch rate than that of an intrinsic form of the semiconductor material. A method of manufacturing a semiconductor device includes forming a gate on a fin, implanting part of the fin with dopants configured to decrease an etch rate of the part of the fin, removing at least part of the fin, and forming an epitaxial semiconductor material on a remaining proximal portion of the fin.

公开(公告)号：US20200211911A1

公开(公告)日：2020-07-02

申请号：US16637932

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Van H. LE ,  Gilbert DEWEY ,  Willy RACHMADY

IPC: H01L21/84 ,  H01L27/12

Abstract: A semiconductor device may include a first gate electrode and a second gate electrode. A first channel area and a second channel area may be above the first gate electrode, where the first channel area may include a first type channel material, and the second channel area may include a second type channel material. A third channel area and a fourth channel area may be above the second gate electrode, where the third channel area may include the first type channel material, and the fourth channel area may include the second type channel material. The third channel area may be separated from the first channel area by a spacer. An inverter may include the first gate electrode, the first channel area, and the second channel area, while another inverter may include the second gate electrode, the third channel area, and the fourth channel area. Other embodiments may be described/claimed.

公开(公告)号：US20200152738A1

公开(公告)日：2020-05-14

申请号：US16740132

申请日：2020-01-10

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Kelin J. KUHN ,  Tahir GHANI ,  Anand S. MURTHY ,  Mark ARMSTRONG ,  Rafael RIOS ,  Abhijit Jayant PETHE ,  Willy RACHMADY

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L21/3115 ,  H01L21/3105 ,  H01L21/306 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

公开(公告)号：US20200006576A1

公开(公告)日：2020-01-02

申请号：US16024701

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Sean MA ,  Nicholas MINUTILLO ,  Cheng-Ying HUANG ,  Tahir GHANI ,  Jack KAVALIEROS ,  Anand MURTHY ,  Harold KENNEL ,  Gilbert DEWEY ,  Matthew METZ ,  Willy RACHMADY

IPC: H01L29/786 ,  H01L29/205 ,  H01L29/423 ,  H01L29/04 ,  H01L29/66

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. A semiconductor device may include isolation areas above a substrate to form a trench between the isolation areas. A first buffer layer is over the substrate, in contact with the substrate, and within the trench. A second buffer layer is within the trench over the first buffer layer, and in contact with the first buffer layer. A channel area is above the first buffer layer, above a portion of the second buffer layer that are below a source area or a drain area, and without being vertically above a portion of the second buffer layer. In addition, the source area or the drain area is above the second buffer layer, in contact with the second buffer layer, and adjacent to the channel area. Other embodiments may be described and/or claimed.