公开(公告)号：US12112200B2

公开(公告)日：2024-10-08

申请号：US17473428

申请日：2021-09-13

Applicant: International Business Machines Corporation

Inventor： Abdullah Kayi ,  Tayfun Gokmen

IPC: G06F9/50 ,  G06N3/08

CPC classification number: G06F9/50 ,  G06N3/08

Abstract: A system comprises compute nodes distributed over a network and configured to perform a pipeline parallel process. The system also comprises an extended memory comprising a global virtual address space which is shared by the compute nodes. The extended memory is configured to enable the compute nodes to exchange data over the network when the compute nodes perform the pipeline parallel process.

公开(公告)号：US11886378B2

公开(公告)日：2024-01-30

申请号：US17135335

申请日：2020-12-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tayfun Gokmen

IPC: G06F15/80 ,  G06F15/78 ,  G06F9/38 ,  G11C13/00 ,  G06N3/04

CPC classification number: G06F15/8007 ,  G06F9/3887 ,  G06F15/7867 ,  G06F15/80 ,  G06F9/3893 ,  G06N3/04 ,  G11C13/0002 ,  G11C13/0007

Abstract: A processor includes an array of resistive processing units connected between row and column lines with a resistive element. A first single instruction, multiple data processing unit (SIMD) is connected to the row lines. A second SIMD is connected to the column lines. A first instruction issuer is connected to the first SIMD to issue instructions to the first SIMD, and a second instruction issuer is connected to the second SIMD to issue instructions to the second SIMD such that the processor is programmable and configurable for specific operations depending on an issued instruction set.

公开(公告)号：US11842770B2

公开(公告)日：2023-12-12

申请号：US17137615

申请日：2020-12-30

Applicant: International Business Machines Corporation

Inventor： Tayfun Gokmen ,  Seyoung Kim ,  Hyung-Min Lee ,  Wooram Lee ,  Paul Michael Solomon

IPC: G11C16/04 ,  G11C13/00 ,  G11C7/10 ,  G11C11/54 ,  G06N3/049 ,  G06N3/084 ,  G06N3/088 ,  G06N3/065 ,  G06N3/02

CPC classification number: G11C13/004 ,  G06N3/02 ,  G06N3/049 ,  G06N3/065 ,  G06N3/084 ,  G06N3/088 ,  G11C7/1006 ,  G11C11/54 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2213/77

Abstract: A processing unit, including a first circuit, and a first circuit element connected to the first circuit. The first circuit element is at least charged by the first circuit.

公开(公告)号：US11574694B2

公开(公告)日：2023-02-07

申请号：US16157848

申请日：2018-10-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Effendi Leobandung ,  Tayfun Gokmen ,  Xiao Sun ,  Yulong Li ,  Malte Rasch

IPC: G11C27/00 ,  G06N3/04 ,  G06N3/063

Abstract: A method for multiple copies of a set of multi-kernel set operations in a hardware accelerated neural network includes a word line for receiving a pixel value of an input image. A bit line communicates a modified pixel value. An analog memory cell including a first capacitor stores a first kernel weight of a first kernel in one of a plurality of kernel sets such that the pixel value is operated on by the first kernel weight to produce the modified pixel value. A charge connection connects the first capacitor to at least a second capacitor storing a second kernel weight of a related kernel of a second one of the plurality of kernel sets such that charge is shared between the first capacitor and at least the second capacitor to normalize the first kernel weight and the second kernel weight.

公开(公告)号：US11574196B2

公开(公告)日：2023-02-07

申请号：US16596716

申请日：2019-10-08

Applicant: International Business Machines Corporation

Inventor： Tayfun Gokmen

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: Machine learning is enhanced by efficiently updating a weight that is represented as a conductivity of a resistive processing unit (RPU) that is connected between a row wire and a column wire. The weight is updated by the RPU interacting with bit streams carried on the row and column wires. Efficiency of the update is enhanced by calculating a bit length for the bit streams as a function of factors that include learning rate η, maximum activity xmax, maximum error differential δmax, and minimum weight update increment Δwmin.

公开(公告)号：US11568217B2

公开(公告)日：2023-01-31

申请号：US16929172

申请日：2020-07-15

Applicant: International Business Machines Corporation

Inventor： Seyoung Kim ,  Oguzhan Murat Onen ,  Tayfun Gokmen ,  Malte Johannes Rasch

IPC: G06N3/04 ,  G06F9/30 ,  G06K9/62 ,  G06N3/063 ,  G06N3/08

Abstract: Provided are embodiments for a computer-implemented method, a system, and a computer program product for updating analog crossbar arrays. The embodiments include receiving a number used in matrix multiplication to represent using pulse generation for a crossbar array, and receiving a first bit-length to represent the number, wherein the bit-length is a modifiable bit length. The embodiments also include selecting pulse positions in a pulse sequence having the first bit length to represent the number, performing a computation using the selected pulse positions in the pulse sequence, and updating the crossbar array using the computation.

公开(公告)号：US20220391681A1

公开(公告)日：2022-12-08

申请号：US17340242

申请日：2021-06-07

Applicant: International Business Machines Corporation

Inventor： Tayfun Gokmen ,  Wilfried Haensch ,  Stefano Ambrogio ,  Charles Mackin

IPC: G06N3/063 ,  G06N10/00 ,  G11C13/00 ,  G06N3/04

Abstract: A system includes a processor, and a resistive processing resistive processing unit coupled to the processor. The resistive processing unit includes an array of cells, wherein the cells respectively include resistive devices, wherein at least a portion of the resistive devices are programmable to store weight values of a given matrix in the array of cells. When the given matrix is stored in the array of cells, the processor is configured to perform a weight extraction process. The weight extraction process applies a set of input vectors to the resistive processing unit to perform analog matrix-vector multiplication operations on the stored matrix, obtains a set of output vectors resulting from the analog matrix-vector multiplication operations, and determines weight values of the given matrix stored in the array of cells utilizing the set of input vectors and the set of output vectors.

公开(公告)号：US20220366005A1

公开(公告)日：2022-11-17

申请号：US17245801

申请日：2021-04-30

Applicant: International Business Machines Corporation

Inventor： Tomasz J. Nowicki ,  Oguzhan Murat Onen ,  Tayfun Gokmen ,  Vasileios Kalantzis ,  Chai Wah Wu ,  Mark S. Squillante ,  Malte Johannes Rasch ,  Wilfried Haensch ,  Lior Horesh

IPC: G06F17/16 ,  G06N3/063

Abstract: Techniques are provided to implement hardware accelerated computing of eigenpairs of a matrix. For example, a system includes a processor, and a resistive processing unit coupled to the processor. The resistive processing unit includes an array of cells which include respective resistive devices, wherein at least a portion of the resistive devices are tunable to encode values of a given matrix which is storable in the array of cells. When the given matrix is stored in the array of cells, the processor is configured to determine an eigenvector of the stored matrix by executing a process which includes performing analog matrix-vector multiplication operations on the stored matrix to converge an initial vector to an estimate of the eigenvector of the stored matrix.

公开(公告)号：US11501148B2

公开(公告)日：2022-11-15

申请号：US16808811

申请日：2020-03-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tayfun Gokmen ,  Seyoung Kim ,  Murat Onen

IPC: G06N3/063 ,  G11C7/16 ,  G06N3/08 ,  G06F17/16 ,  G11C11/54 ,  G11C13/00

Abstract: A device configured to implement an artificial intelligence deep neural network includes a first matrix and a second matrix. The first matrix resistive processing unit (“RPU”) array receives a first input vector along the rows of the first matrix RPU. A second matrix RPU array receives a second input vector along the rows of the second matrix RPU. A reference matrix RPU array receives an inverse of the first input vector along the rows of the reference matrix RPU and an inverse of the second input vector along the rows of the reference matrix RPU. A plurality of analog to digital converters are coupled to respective outputs of a plurality of summing junctions that receive respective column outputs of the first matrix RPU array, the second matrix RPU array, and the reference RPU array and provides a digital value of the output of the plurality of summing junctions.

公开(公告)号：US11133063B1

公开(公告)日：2021-09-28

申请号：US16907437

申请日：2020-06-22

Applicant: International Business Machines Corporation

Inventor： Seyoung Kim ,  Oguzhan Murat Onen ,  Tayfun Gokmen

IPC: G11C16/04 ,  G11C16/10 ,  G11C13/00 ,  G06N3/04 ,  G06N3/063

Abstract: Aspects of the invention include performing a stochastic update for a crossbar array by generating a set of stochastic pulses for a crossbar array, the crossbar array including a plurality of row wires and a plurality of column wires, the plurality of row wires including a first row wire and the plurality of column wires including a first column wire, wherein a three terminal device is coupled to the first row wire and the first column wire at a crosspoint of the first row wire and the first column wire, and wherein a resistivity of the three terminal device is modified responsive to a coincidence of pulses from the set of stochastic pulses at the crosspoint of the first row and the first column, and wherein at least one terminal in the three terminal device is floating.