Abstract:
Disclosed are semiconductor structures with metal lines and methods of manufacture which reduce or eliminate extrusion formation. The method includes forming a metal wiring comprising a layered structure of metal materials with an upper constraining layer. The method further includes forming a film on the metal wiring which prevents metal extrusion during an annealing process.
Abstract:
Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer adjacent the aluminum island. The opening includes a lateral extrusion of the aluminum layer of the semiconductor structure. Additional embodiments include a method of forming a semiconductor structure. The method can include forming an aluminum layer over a titanium layer. The aluminum layer includes an aluminum island within the aluminum layer. The method can also include forming an opening extending through the aluminum layer adjacent the aluminum island within the aluminum layer. The opening includes a lateral extrusion of the aluminum layer of the semiconductor layer.
Abstract:
A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.
Abstract:
Semiconductor devices with enhanced electromigration performance and methods of manufacture are disclosed. The method includes forming at least one metal line in electrical contact with a device. The method further includes forming at least one staple structure in electrical contact with the at least one metal line. The at least one staple structure is formed such that electrical current passing through the at least one metal line also passes through the at least staple structure to reduce electromigration issues.