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    Method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof
    2.
    发明授权
    Method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof 有权
    减少半导体结构中形成的横向挤压的方法和由其形成的半导体结构

    公开(公告)号：US09006703B2

    公开(公告)日：2015-04-14

    申请号：US13955531

    申请日：2013-07-31

    Applicant: International Business Machines Corporation

    Inventor： Shawn A. Adderly ,  Brian M. Czabaj ,  Daniel A. Delibac ,  Jeffrey P. Gambino ,  Matthew D. Moon ,  David C. Thomas

    IPC: H01L21/00 ,  H01L49/02 ,  H01L21/66

    CPC classification number: H01L28/40 ,  H01L22/12 ,  H01L22/20

    Abstract: Aspects of the present invention relate to method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof. Various embodiments include a method for reducing lateral extrusion formed in semiconductor structures. The method can include removing a portion of a first lateral extrusion in an aluminum layer of the semiconductor structure, and determining a post-removal thickness of a dielectric layer positioned adjacent the aluminum layer. The post-removal thickness may be determined subsequent to the removing of the portion of the first lateral extrusion. The method can also include determining a difference between the post-removal thickness of the dielectric layer and a pre-removal thickness of the dielectric layer.

    Abstract translation: 本发明的方面涉及减少由半导体结构形成的侧向挤出和由其形成的半导体结构的方法。 各种实施例包括用于减少在半导体结构中形成的横向挤压的方法。 该方法可以包括去除半导体结构的铝层中的第一侧向挤压的一部分，以及确定位于铝层附近的电介质层的去除后厚度。 去除后厚度可以在去除第一侧向挤出部分的部分之后确定。 该方法还可以包括确定介电层的去除后厚度与介电层的去除去除厚度之间的差异。

    METHOD FOR REDUCING LATERAL EXTRUSION FORMED IN SEMICONDUCTOR STRUCTURES AND SEMICONDUCTOR STRUCTURES FORMED THEREOF
    3.
    发明申请
    METHOD FOR REDUCING LATERAL EXTRUSION FORMED IN SEMICONDUCTOR STRUCTURES AND SEMICONDUCTOR STRUCTURES FORMED THEREOF 有权
    用于减少半导体结构形成的侧向挤出的方法及其形成的半导体结构

    公开(公告)号：US20150035117A1

    公开(公告)日：2015-02-05

    申请号：US13955531

    申请日：2013-07-31

    Applicant: International Business Machines Corporation

    Inventor： Shawn A. Adderly ,  Brian M. Czabaj ,  Daniel A. Delibac ,  Jeffrey P. Gambino ,  Matthew D. Moon ,  David C. Thomas

    IPC: H01L49/02 ,  H01L21/66

    CPC classification number: H01L28/40 ,  H01L22/12 ,  H01L22/20

    Abstract: Aspects of the present invention relate to method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof. Various embodiments include a method for reducing lateral extrusion formed in semiconductor structures. The method can include removing a portion of a first lateral extrusion in an aluminum layer of the semiconductor structure, and determining a post-removal thickness of a dielectric layer positioned adjacent the aluminum layer. The post-removal thickness may be determined subsequent to the removing of the portion of the first lateral extrusion. The method can also include determining a difference between the post-removal thickness of the dielectric layer and a pre-removal thickness of the dielectric layer.

    Abstract translation: 本发明的方面涉及减少由半导体结构形成的侧向挤出和由其形成的半导体结构的方法。 各种实施例包括用于减少在半导体结构中形成的横向挤压的方法。 该方法可以包括去除半导体结构的铝层中的第一侧向挤压的一部分，以及确定位于铝层附近的电介质层的去除后厚度。 去除后厚度可以在去除第一侧向挤出部分的部分之后确定。 该方法还可以包括确定介电层的去除后厚度与介电层的去除去除厚度之间的差异。

    Method of fine-tuning process controls during integrated circuit chip manufacturing based on substrate backside roughness
    4.
    发明授权
    Method of fine-tuning process controls during integrated circuit chip manufacturing based on substrate backside roughness 有权
    基于衬底背面粗糙度的集成电路芯片制造过程中微调过程控制的方法

    公开(公告)号：US09330988B1

    公开(公告)日：2016-05-03

    申请号：US14580283

    申请日：2014-12-23

    Applicant: International Business Machines Corporation

    Inventor： Shawn A. Adderly ,  Kyle Babinski ,  Daniel A. Delibac ,  David A. DeMuynck ,  Shawn R. Goddard ,  Matthew D. Moon ,  Melissa J. Roma ,  Craig E. Schneider

    IPC: H01L21/66 ,  H01L21/3213

    CPC classification number: H01L22/22 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/32139 ,  H01L22/12 ,  H01L22/20

    Abstract: Disclosed is a method of manufacturing integrated circuit (IC) chips. In the method, wafers are received and the backside roughness levels of these wafers are determined. Based on the backside roughness levels, the wafers are sorted into different groups. Chips having the same design are manufactured on wafers from all of the different groups. However, during manufacturing, process(es) is/are performed differently on wafers from one or more of the different groups to minimize systematic variations in a specific parameter (e.g., wire width) in the resulting chips. Specifically, because systematic variations may occur when the exact same processes are used to form IC chips on wafers with different backside roughness levels, the method disclosed herein selectively adjusts one or more of those processes when performed on wafers from one or more of the different groups to ensure that the specific parameter is approximately equal in the resulting integrated IC chips.

    Abstract translation: 公开了一种制造集成电路（IC）芯片的方法。 在该方法中，接收晶片并确定这些晶片的背面粗糙度水平。 基于背面粗糙度水平，将晶片分成不同的组。 具有相同设计的芯片在来自所有不同组的晶片上制造。 然而，在制造过程中，在来自一个或多个不同组的晶片上进行不同的处理，以最小化所得芯片中的特定参数（例如，线宽）的系统变化。 具体地说，因为当使用完全相同的工艺在具有不同背面粗糙度水平的晶片上形成IC芯片时，可能发生系统的变化，所以当在一个或多个不同的组中对晶片执行时，这里所公开的方法选择性地调节这些工艺中的一个或多个 以确保在所得到的集成IC芯片中的具体参数近似相等。

    Method of fine-tuning process controls during integrated circuit chip manufacturing based on substrate backside roughness
    5.
    发明授权
    Method of fine-tuning process controls during integrated circuit chip manufacturing based on substrate backside roughness 有权
    基于衬底背面粗糙度的集成电路芯片制造过程中微调过程控制的方法

    公开(公告)号：US09576863B2

    公开(公告)日：2017-02-21

    申请号：US14966389

    申请日：2015-12-11

    Applicant: International Business Machines Corporation

    Inventor： Shawn A. Adderly ,  Kyle Babinski ,  Daniel A. Delibac ,  David A. DeMuynck ,  Shawn R. Goddard ,  Matthew D. Moon ,  Melissa J. Roma ,  Craig E. Schneider

    IPC: H01L21/3065 ,  H01L21/66 ,  H01L21/3213 ,  H01L21/308 ,  H01L21/311

    CPC classification number: H01L22/22 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/32139 ,  H01L22/12 ,  H01L22/20

    Abstract: Disclosed is a method of manufacturing integrated circuit (IC) chips. In the method, wafers are received and the backside roughness levels of these wafers are determined. Based on the backside roughness levels, the wafers are sorted into different groups. Chips having the same design are manufactured on wafers from all of the different groups. However, during manufacturing, process(es) is/are performed differently on wafers from one or more of the different groups to minimize systematic variations in a specific parameter (e.g., wire width) in the resulting chips. Specifically, because systematic variations may occur when the exact same processes are used to form IC chips on wafers with different backside roughness levels, the method disclosed herein selectively adjusts one or more of those processes when performed on wafers from one or more of the different groups to ensure that the specific parameter is approximately equal in the resulting integrated IC chips.

    Abstract translation: 公开了一种制造集成电路（IC）芯片的方法。 在该方法中，接收晶片并确定这些晶片的背面粗糙度水平。 基于背面粗糙度水平，将晶片分成不同的组。 具有相同设计的芯片在来自所有不同组的晶片上制造。 然而，在制造过程中，在来自一个或多个不同组的晶片上进行不同的处理，以最小化所得芯片中的特定参数（例如，线宽）的系统变化。 具体地说，因为当使用完全相同的工艺在具有不同背面粗糙度水平的晶片上形成IC芯片时，可能发生系统的变化，所以当在一个或多个不同的组中对晶片执行时，这里所公开的方法选择性地调节这些工艺中的一个或多个 以确保所得到的集成IC芯片中的特定参数近似相等。

    METHOD OF FINE-TUNING PROCESS CONTROLS DURING INTEGRATED CIRCUIT CHIP MANUFACTURING BASED ON SUBSTRATE BACKSIDE ROUGHNESS
    6.
    发明申请
    METHOD OF FINE-TUNING PROCESS CONTROLS DURING INTEGRATED CIRCUIT CHIP MANUFACTURING BASED ON SUBSTRATE BACKSIDE ROUGHNESS 有权
    基于底层粗糙度的集成电路芯片制造过程中的微调过程控制方法

    公开(公告)号：US20160181166A1

    公开(公告)日：2016-06-23

    申请号：US14966389

    申请日：2015-12-11

    Applicant: International Business Machines Corporation

    Inventor： Shawn A. Adderly ,  Kyle Babinski ,  Daniel A. Delibac ,  David A. DeMuynck ,  Shawn R. Goddard ,  Matthew D. Moon ,  Melissa J. Roma ,  Craig E. Schneider

    IPC: H01L21/66 ,  H01L21/3065 ,  H01L21/308

    CPC classification number: H01L22/22 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/32139 ,  H01L22/12 ,  H01L22/20

    Abstract: Disclosed is a method of manufacturing integrated circuit (IC) chips. In the method, wafers are received and the backside roughness levels of these wafers are determined. Based on the backside roughness levels, the wafers are sorted into different groups. Chips having the same design are manufactured on wafers from all of the different groups. However, during manufacturing, process(es) is/are performed differently on wafers from one or more of the different groups to minimize systematic variations in a specific parameter (e.g., wire width) in the resulting chips. Specifically, because systematic variations may occur when the exact same processes are used to form IC chips on wafers with different backside roughness levels, the method disclosed herein selectively adjusts one or more of those processes when performed on wafers from one or more of the different groups to ensure that the specific parameter is approximately equal in the resulting integrated IC chips.

    Abstract translation: 公开了一种制造集成电路（IC）芯片的方法。 在该方法中，接收晶片并确定这些晶片的背面粗糙度水平。 基于背面粗糙度水平，将晶片分成不同的组。 具有相同设计的芯片在来自所有不同组的晶片上制造。 然而，在制造过程中，在来自一个或多个不同组的晶片上进行不同的处理，以最小化所得芯片中的特定参数（例如，线宽）的系统变化。 具体地说，因为当使用完全相同的工艺在具有不同背面粗糙度水平的晶片上形成IC芯片时，可能发生系统的变化，所以当在一个或多个不同的组中对晶片执行时，这里所公开的方法选择性地调节这些工艺中的一个或多个 以确保所得到的集成IC芯片中的特定参数近似相等。

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