公开(公告)号：US11024547B2

公开(公告)日：2021-06-01

申请号：US16684916

申请日：2019-11-15

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L29/423 ,  H01L29/786

Abstract: A method for manufacturing a semiconductor device includes forming a fin on a substrate, removing one or more portions of the fin prior to forming a gate structure on the fin, forming the gate structure on the fin, and simultaneously removing one or more additional portions of the fin and one or more portions of the gate structure aligned with the one or more additional portions of the fin to create a fin edge portion aligned with a gate structure edge portion.

公开(公告)号：US11022891B2

公开(公告)日：2021-06-01

申请号：US15800786

申请日：2017-11-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Karen E. Petrillo ,  Nicole A. Saulnier ,  Hao Tang

IPC: G03F7/32 ,  G03F7/40

Abstract: A method for removing photoresist bridging defects includes coating a photoresist layer over a dielectric layer formed over a substrate, applying a first developer that results in formation of one or more photoresist bridging defects, and applying a second developer to remove the one or more photoresist bridging defects. The first developer is an aqueous base developer and the second developer is a reverse tone weak developer (RTWD), the RTWD being a mixture of a first (good) solvent and a second (bad) solvent for the photoresist.

公开(公告)号：US11022890B2

公开(公告)日：2021-06-01

申请号：US15440198

申请日：2017-02-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Karen E. Petrillo ,  Nicole A. Saulnier ,  Hao Tang

IPC: G06F7/32 ,  G03F7/32 ,  G03F7/40

Abstract: A method for removing photoresist bridging defects includes coating a photoresist layer over a dielectric layer formed over a substrate, applying a first developer that results in formation of one or more photoresist bridging defects, and applying a second developer to remove the one or more photoresist bridging defects. The first developer is an aqueous base developer and the second developer is a reverse tone weak developer (RTWD), the RTWD being a mixture of a first (good) solvent and a second (bad) solvent for the photoresist.

公开(公告)号：US11004751B2

公开(公告)日：2021-05-11

申请号：US16284261

申请日：2019-02-25

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  Dexin Kong ,  Zhenxing Bi

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L27/088 ,  H01L21/311 ,  H01L29/06 ,  H01L21/308 ,  H01L21/3065

Abstract: A semiconductor device includes a substrate with a first semiconductor fin and a second semiconductor fin formed thereon. A pair of opposing dielectric trench spacers are between the first and second semiconductor fins. The opposing dielectric trench spacers define an isolation region therebetween. The semiconductor device further includes a shallow trench isolation (STI) element formed in the isolation region. The STI element includes a lower portion on the substrate and an upper portion located opposite the lower portion. The upper portion extends above an upper end of the dielectric trench spacers.

公开(公告)号：US10957601B2

公开(公告)日：2021-03-23

申请号：US16157588

申请日：2018-10-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Wenyu Xu ,  Xin Miao

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L21/3065 ,  H01L29/51 ,  H01L21/02

Abstract: Semiconductor devices and methods of forming the same include etching a stack of alternating channel and sacrificial layers to form a fin. The etch depth is controlled by a signal layer embedded in a substrate under the stack. Source and drain regions are formed on ends of the channel layers. The sacrificial layers are etched away and a gate stack is formed over and between the channel layers.

公开(公告)号：US10937792B2

公开(公告)日：2021-03-02

申请号：US16431451

申请日：2019-06-04

Applicant: International Business Machines Corporation

Inventor： Peng Xu ,  Kangguo Cheng ,  Zhenxing Bi ,  Juntao Li

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: A configuration of components formed on a semiconductor structure is provided. A non-limiting example of the configuration includes a substrate having a first section doped with a first dopant and a second section doped with a second dopant. The configuration further includes an insulator interposed between the first and second sections. A first fin extends upwardly from the first section, and second and third fins extend upwardly from the second section. A conductor is configured to be shared between proximal gates operably interposed between the first and second fins. A dielectric material is configured to separate proximal gates operably interposed between the second and third fins.

公开(公告)号：US10937703B2

公开(公告)日：2021-03-02

申请号：US16381129

申请日：2019-04-11

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/161 ,  H01L29/10

Abstract: An integrated semiconductor device having a substrate with a first substrate region and a second substrate region. The integrated semiconductor device further includes a first field-effect transistor disposed on the substrate in the first substrate region. The first field-effect transistor has a plurality of first fins having a first semiconductor material. In addition, the integrated semiconductor device includes a second field-effect transistor disposed on the substrate in the second substrate region. The second field-effect transistor has a plurality of second fins having a second semiconductor material that differs from the first semiconductor material.

公开(公告)号：US10930734B2

公开(公告)日：2021-02-23

申请号：US16174603

申请日：2018-10-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Zhenxing Bi ,  Kangguo Cheng ,  Zheng Xu

IPC: H01L29/06 ,  H01L29/08 ,  H01L21/762 ,  H01L21/02

Abstract: A technique relates to a semiconductor device. A rare earth material is formed on a substrate. An isolation layer is formed at an interface of the rare earth material and the substrate. Channel layers are formed over the isolation layer. Source or drain (S/D) regions are formed on the isolation layer.

公开(公告)号：US10890560B2

公开(公告)日：2021-01-12

申请号：US15985266

申请日：2018-05-21

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Kangguo Cheng ,  Peng Xu ,  Zhenxing Bi

IPC: G01N27/447 ,  B82B3/00 ,  G01N33/487 ,  B82B1/00 ,  B82Y40/00 ,  B82Y15/00

Abstract: A method of forming a semiconductor structure includes forming two or more catalyst nanoparticles from a metal layer disposed over a substrate in two or more openings of a hard mask patterned over the metal layer. The method also includes growing two or more carbon nanotubes using the catalyst nanoparticles, and removing the carbon nanotubes to form two or more nanoscale pores. The two or more nanoscale pores may be circular nanoscale pores having a substantially uniform diameter. The two or more openings in the hard mask may have non-uniform size, and the substantially uniform diameter of the two or more nanopores may be controlled by a size of the carbon nanotubes.

公开(公告)号：US10804274B2

公开(公告)日：2020-10-13

申请号：US16286843

申请日：2019-02-27

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Zheng Xu ,  Dexin Kong ,  Kangguo Cheng

IPC: H01L21/44 ,  H01L27/105 ,  H01L21/8229 ,  H01L29/06

Abstract: A method of performing co-integrated fabrication of a non-volatile memory (NVM) and a gate-all-around (GAA) nanosheet field effect transistor (FET) includes recessing fins in a channel region of the NVM and the FET to form source and drain regions adjacent to recessed fins, and removing alternating portions of the recessed fins of the NVM and the FET to form gaps in the recessed fins. A stack of layers that make up an NVM structure are conformally deposited within the gaps of the recessed fins leaving second gaps, smaller than the gaps, and above the recessed fins of the NVM while protecting the FET with the organic planarization layer (OPL) and a block mask. The OPL and block mask are removed from the FET, and another OPL and another block mask protect the NVM while a gate of the FET is formed above the recessed fins and within the gaps.