公开(公告)号：US20200185532A1

公开(公告)日：2020-06-11

申请号：US16214706

申请日：2018-12-10

Applicant: INTEL CORPORATION

Inventor： Kevin Lin ,  Abhishek Sharma ,  Carl Naylor ,  Urusa Alaan ,  Christopher Jezewski ,  Ashish Agrawal

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/24 ,  H01L29/417

Abstract: A transistor structure includes a layer of active material on a base. The base can be insulator material in some cases. The layer has a channel region between a source region and a drain region. A gate structure is in contact with the channel region and includes a gate electrode and a gate dielectric, where the gate dielectric is between the gate electrode and the active material. An electrical contact is on one or both of the source region and the drain region. The electrical contact has a larger portion in contact with a top surface of the active material and a smaller portion extending through the layer of active material into the base. The active material may be, for example, a transition metal dichalcogenide (TMD) in some embodiments.

公开(公告)号：US12266570B2

公开(公告)日：2025-04-01

申请号：US17133065

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Souvik Ghosh ,  Willy Rachmady ,  Ashish Agrawal ,  Siddharth Chouksey ,  Jessica Torres ,  Jack Kavalieros ,  Matthew Metz ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H10B61/00 ,  H10B63/00

Abstract: An integrated circuit interconnect structure includes a metallization level above a first device level. The metallization level includes an interconnect structure coupled to the device structure, a conductive cap including an alloy of a metal of the interconnect structure and either silicon or germanium on an uppermost surface of the interconnect structure. A second device level above the conductive cap includes a transistor coupled with the conductive cap. The transistor includes a channel layer including a semiconductor material, where at least one sidewall of the conductive cap is co-planar with a sidewall of the channel layer. The transistor further includes a gate on a first portion of the channel layer, where the gate is between a source region and a drain region, where one of the source or the drain region is in contact with the conductive cap.

公开(公告)号：US12199142B2

公开(公告)日：2025-01-14

申请号：US17133092

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Siddharth Chouksey ,  Jack T. Kavalieros ,  Stephen M. Cea ,  Ashish Agrawal ,  Willy Rachmady

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: Neighboring gate-all-around integrated circuit structures having a conductive contact stressor between epitaxial source or drain regions are described. In an example, a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening conductive contact structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures. The intervening conductive contact structure imparts a stress to the neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.

公开(公告)号：US11929320B2

公开(公告)日：2024-03-12

申请号：US17709032

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Ryan Keech ,  Cory Bomberger ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Willy Rachmady ,  Anand Murthy

IPC: H01L29/74 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L27/12

CPC classification number: H01L23/5226 ,  H01L21/76251 ,  H01L21/76804 ,  H01L27/1203

Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

公开(公告)号：US11862715B2

公开(公告)日：2024-01-02

申请号：US17745822

申请日：2022-05-16

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Willy Rachmady ,  Uygar Avci ,  Ashish Agrawal ,  Benjamin Chu-Kung

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/66977 ,  H01L29/0649 ,  H01L29/41733 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696

Abstract: Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.

公开(公告)号：US20230197569A1

公开(公告)日：2023-06-22

申请号：US17556711

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Cheng-Ying Huang ,  Nicole K. Thomas ,  Marko Radosavljevic ,  Patrick Morrow ,  Ashish Agrawal ,  Willy Rachmady ,  Seung Hoon Sung ,  Christopher M. Neumann

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L21/8234

CPC classification number: H01L23/481 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/78696 ,  H01L29/42392 ,  H01L21/823475

Abstract: Techniques are provided herein to form semiconductor devices having a frontside and backside contact in an epi region of a stacked transistor configuration. In one example, an n-channel device and a p-channel device may both be GAA transistors where the n-channel device is located vertically above the p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and the p-channel device. Deep and narrow contacts may be formed from both the frontside and the backside of the integrated circuit through the stacked source or drain regions. The contacts may physically contact each other to form a combined contact that extends through an entirety of the stacked source or drain regions. The higher contact area provided to both source or drain regions provides a more robust ohmic contact with a lower contact resistance compared to previous contact architectures.

公开(公告)号：US20230147499A1

公开(公告)日：2023-05-11

申请号：US17523710

申请日：2021-11-10

Applicant: Intel Corporation

Inventor： Ashish Agrawal ,  Anand Murthy ,  Jack T. Kavalieros ,  Rajat K. Paul ,  Gilbert Dewey ,  Seung Hoon Sung ,  Susmita Ghose

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78687

Abstract: Techniques are provided herein to form semiconductor devices having strained channel regions. In an example, semiconductor nanoribbons of silicon germanium (SiGe) or germanium tin (GeSn) may be formed and subsequently annealed to drive the germanium or tin inwards along a portion of the semiconductor nanoribbons thus increasing the germanium or tin concentration through a central portion along the lengths of the one or more nanoribbons. Specifically, a nanoribbon may have a first region at one end of the nanoribbon having a first germanium concentration, a second region at the other end of the nanoribbon having substantially the same first germanium concentration (e.g., within 5%), and a third region between the first and second regions having a second germanium concentration higher than the first concentration. A similar material gradient may also be created using tin. The change in material composition (gradient) along the nanoribbon length imparts a compressive strain.

公开(公告)号：US11575005B2

公开(公告)日：2023-02-07

申请号：US15942252

申请日：2018-03-30

Applicant: INTEL CORPORATION

Inventor： Seung Hoon Sung ,  Dipanjan Basu ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Siddharth Chouksey ,  Cory C. Bomberger ,  Tahir Ghani ,  Anand S. Murthy ,  Jack T. Kavalieros

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16

Abstract: An integrated circuit structure includes: a semiconductor nanowire extending in a length direction and including a body portion; a gate dielectric surrounding the body portion; a gate electrode insulated from the body portion by the gate dielectric; a semiconductor source portion adjacent to a first side of the body portion; and a semiconductor drain portion adjacent to a second side of the body portion opposite the first side, the narrowest dimension of the second side of the body portion being smaller than the narrowest dimension of the first side. In an embodiment, the nanowire has a conical tapering. In an embodiment, the gate electrode extends along the body portion in the length direction to the source portion, but not to the drain portion. In an embodiment, the drain portion at the second side of the body portion has a lower dopant concentration than the source portion at the first side.

公开(公告)号：US20220375916A1

公开(公告)日：2022-11-24

申请号：US17323425

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Gilbert W. Dewey ,  Jack T. Kavalieros ,  Abhishek A. Sharma ,  Willy Rachmady

IPC: H01L25/18 ,  H01L25/065 ,  H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Described herein are IC devices that include multilayer memory structures bonded to compute logic using low-temperature oxide bonding to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM). An example device includes a compute die, a multilayer memory structure, and an oxide bonding interface coupling the compute die to the multilayer memory structure. The oxide bonding interface includes metal interconnects and an oxide material surrounding the metal interconnects and bonding the compute die to the memory structure.

公开(公告)号：US20220199624A1

公开(公告)日：2022-06-23

申请号：US17132981

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Ashish Agrawal ,  Gilbert Dewey ,  Abhishek A. Sharma ,  Wilfred Gomes ,  Jack Kavalieros

IPC: H01L27/108 ,  H01L27/11507 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/683

Abstract: Monolithic two-dimensional (2D) arrays of double-sided DRAM cells including a frontside bit cell over a backside bit cell. Each double-sided cell includes a stacked transistor structure having at least a first transistor over a second transistor. Each double-sided cell further includes a first capacitor on a frontside of the stacked transistor structure and electrically coupled to a source/drain of the first transistor. Each double-sided cell further includes a second capacitor on a backside of the stacked transistor structure and electrically coupled to a source/drain of the second transistor. Frontside cell addressing interconnects are electrically coupled to other terminals of at least the first transistor while one or more backside addressing interconnects are electrically coupled to at least one terminal of the second transistor or second capacitor.