公开(公告)号：US10884957B2

公开(公告)日：2021-01-05

申请号：US16160952

申请日：2018-10-15

Applicant: Intel Corporation

Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor W. Lee ,  Abhishek Sharma ,  Huseyin E. Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young

IPC: G06F13/16 ,  G06F13/28 ,  G06N20/00

Abstract: Techniques and mechanisms for performing in-memory computations with circuitry having a pipeline architecture. In an embodiment, various stages of a pipeline each include a respective input interface and a respective output interface, distinct from said input interface, to couple to different respective circuitry. These stages each further include a respective array of memory cells and circuitry to perform operations based on data stored by said array. A result of one such in-memory computation may be communicated from one pipeline stage to a respective next pipeline stage for use in further in-memory computations. Control circuitry, interconnect circuitry, configuration circuitry or other logic of the pipeline precludes operation of the pipeline as a monolithic, general-purpose memory device. In other embodiments, stages of the pipeline each provide a different respective layer of a neural network.

公开(公告)号：US10748603B2

公开(公告)日：2020-08-18

申请号：US16146473

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram Krishnamurthy ,  Ian A. Young

IPC: G11C8/00 ,  G11C11/418 ,  G06F9/30 ,  G11C11/419 ,  G11C13/00 ,  G11C7/10 ,  G11C11/54 ,  G06N3/063 ,  G06N3/08 ,  G11C7/18 ,  G06F7/544 ,  G11C11/16

Abstract: A memory circuit has compute-in-memory circuitry that enables a multiply-accumulate (MAC) operation based on shared charge. Row access circuitry drives multiple rows of a memory array to multiply a first data word with a second data word stored in the memory array. The row access circuitry drives the multiple rows based on the bit pattern of the first data word. Column access circuitry drives a column of the memory array when the rows are driven. Accessed rows discharge the column line in an accumulative fashion. Sensing circuitry can sense voltage on the column line. A processor in the memory circuit computes a MAC value based on the voltage sensed on the column.

公开(公告)号：US20200242458A1

公开(公告)日：2020-07-30

申请号：US16258522

申请日：2019-01-25

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Ram Krishnamurthy ,  Amrita Mathuriya ,  Dmitri Nikonov ,  Ian Young

IPC: G06N3/063 ,  G06F17/16 ,  G06N3/04

Abstract: Techniques are provided for implementing a hybrid processing architecture comprising a general-purpose processor (CPU) coupled to an analog in-memory artificial intelligence (AI) processor. A hybrid processor implementing the techniques according to an embodiment includes an AI processor configured to perform analog in-memory computations based on neural network (NN) weighting factors and input data provided by the CPU. The AI processor includes one or more NN layers. The NN layers include digital access circuits to receive data and weighting factors and to provide computational results. The NN layers also include memory circuits to store data and weights, and further include bit line processors and cross bit line processors to perform analog dot product computations between columns of the data memory circuits and the weight factor memory circuits. Some of the NN layers are configured as convolutional NN layers and others are configured as fully connected NN layers, according to some embodiments.

公开(公告)号：US20200150179A1

公开(公告)日：2020-05-14

申请号：US16681691

申请日：2019-11-12

Applicant: Intel Corporation

Inventor： Amit Agarwal ,  Ram Krishnamurthy ,  Satish Damaraju ,  Steven Hsu ,  Simeon Realov

IPC: G01R31/317 ,  G01R31/3185 ,  H03K3/037 ,  G01R31/3177

Abstract: An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.

公开(公告)号：US10473718B2

公开(公告)日：2019-11-12

申请号：US15846047

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Amit Agarwal ,  Ram Krishnamurthy ,  Satish Damaraju ,  Steven Hsu ,  Simeon Realov

IPC: G01R31/317 ,  G01R31/3177 ,  H03K3/037 ,  G01R31/3185

Abstract: An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.

公开(公告)号：US10284368B2

公开(公告)日：2019-05-07

申请号：US15399568

申请日：2017-01-05

Applicant: Intel Corporation

Inventor： Jiangtao Li ,  Anand Rajan ,  Roel Maes ,  Sanu K Mathew ,  Ram Krishnamurthy ,  Ernie Brickell

IPC: H04L29/06 ,  H04L9/08 ,  G09C1/00

Abstract: Some implementations disclosed herein provide techniques and arrangements for provisioning keys to integrated circuits/processor. In one embodiments, a key provisioner/tester apparatus may include a memory device to receive a unique hardware key generated by a first logic of a processor. The key provisioner/tester apparatus may further include a cipher device to permanently store an encrypted first key in nonvolatile memory of the processor, detect whether the stored encrypted first key is valid, and to isolate at least one of the first logic and the nonvolatile memory of the processor from all sources that are exterior to the processor in response to detecting that the stored encrypted first key is valid.

公开(公告)号：US20170195116A1

公开(公告)日：2017-07-06

申请号：US14569428

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Michael E. Kounavis ,  Shay Gueron ,  Ram Krishnamurthy ,  Sanu K. Mathew

IPC: H04L9/06 ,  G06F9/38 ,  G06F21/60 ,  G06F9/30

CPC classification number: H04L9/0631 ,  G06F7/00 ,  G06F9/30007 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30196 ,  G06F9/3887 ,  G06F21/602 ,  H04L2209/34

Abstract: Implementations of Advanced Encryption Standard (AES) encryption and decryption processes are disclosed. In one embodiment of S-box processing, a block of 16 byte values is converted, each byte value being converted from a polynomial representation in GF(256) to a polynomial representation in GF((22)4). Multiplicative inverse polynomial representations in GF((22)4) are computed for each of the corresponding polynomial representations in GF((22)4). Finally corresponding multiplicative inverse polynomial representations in GF((22)4) are converted and an affine transformation is applied to generate corresponding polynomial representations in GF(256). In an alternative embodiment of S-box processing, powers of the polynomial representations are computed and multiplied together in GF(256) to generate multiplicative inverse polynomial representations in GF(256). In an embodiment of inverse-columns-mixing, the 16 byte values are converted from a polynomial representation in GF(256) to a polynomial representation in GF((24)2). A four-by-four matrix is applied to the transformed polynomial representation in GF((24)2) to implement the inverse-columns-mixing.

公开(公告)号：US20170126405A1

公开(公告)日：2017-05-04

申请号：US15399568

申请日：2017-01-05

Applicant: Intel Corporation

Inventor： Jiangtao Li ,  Anand Rajan ,  Roel Maes ,  Sanu K Mathew ,  Ram Krishnamurthy ,  Ernie Brickell

IPC: H04L9/08

CPC classification number: H04L9/0891 ,  G09C1/00 ,  H04L9/0822 ,  H04L9/0861 ,  H04L9/0866 ,  H04L9/0894 ,  H04L2209/12

Abstract: Some implementations disclosed herein provide techniques and arrangements for provisioning keys to integrated circuits/processor. In one embodiments, a key provisioner/tester apparatus may include a memory device to receive a unique hardware key generated by a first logic of a processor. The key provisioner/tester apparatus may further include a cipher device to permanently store an encrypted first key in nonvolatile memory of the processor, detect whether the stored encrypted first key is valid, and to isolate at least one of the first logic and the nonvolatile memory of the processor from all sources that are exterior to the processor in response to detecting that the stored encrypted first key is valid.

公开(公告)号：US20160261252A1

公开(公告)日：2016-09-08

申请号：US14635849

申请日：2015-03-02

Applicant: Intel Corporation

Inventor： Amit Agarwal ,  Steven Hsu ,  Ram Krishnamurthy

IPC: H03K3/356 ,  H03K3/3562

CPC classification number: H03K3/356008 ,  H03K3/012 ,  H03K3/0372 ,  H03K3/35625

Abstract: Embodiments include apparatuses, methods, and systems for state retention electronic devices. In embodiments, an electronic device may include a state retention flip-flop having a plurality of P-type metal oxide semiconductor (PMOS) devices coupled with a common N-well, with one or more of the plurality of PMOS devices powered by an always-on supply and one or more of the plurality of PMOS devices powered by a power-gated supply. Other embodiments may be described and claimed.

Abstract translation: 实施例包括用于状态保持电子设备的装置，方法和系统。 在实施例中，电子设备可以包括状态保持触发器，其具有与公共N阱耦合的多个P型金属氧化物半导体（PMOS）器件，其中一个或多个PMOS器件由始终 并且由电源门控电源供电的多个PMOS器件中的一个或多个。 可以描述和要求保护其他实施例。