公开(公告)号：US11107781B2

公开(公告)日：2021-08-31

申请号：US16481392

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Rahul N. Manepalli ,  Kristof Kuwawi Darmawikarta ,  Robert Alan May ,  Aleksandar Aleksov ,  Telesphor Kamgaing

IPC: H01L23/66 ,  H01L21/56 ,  H01L23/00

Abstract: Semiconductor packages having a die electrically connected to an antenna by a coaxial interconnect are described. In an example, a semiconductor package includes a molded layer between a first antenna patch and a second antenna patch of the antenna. The first patch may be electrically connected to the coaxial interconnect, and the second patch may be mounted on the molded layer. The molded layer may be formed from a molding compound, and may have a stiffness to resist warpage during fabrication and use of the semiconductor package.

公开(公告)号：US11107780B2

公开(公告)日：2021-08-31

申请号：US16435136

申请日：2019-06-07

Applicant: Intel Corporation

Inventor： Lilia May ,  Robert Alan May ,  Amruthavalli Pallavi Alur ,  Robert L. Sankman

IPC: H01L23/66 ,  H05K1/02 ,  H01L23/00 ,  H01L23/522

Abstract: An integrated-circuit package substrate includes a pseudo-stripline that is shielded below a lower solder-resist layer and an upper solder-resist layer, where an upper shielding plane is sandwiched between the lower and upper solder-resist layers. The lower solder-resist layer can at least partially overlap a landing-pad region of a landing-pad via that penetrates a top build-up layer which is contacted by the lower solder-resist layer.

公开(公告)号：US10854541B2

公开(公告)日：2020-12-01

申请号：US16554008

申请日：2019-08-28

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Jung Kyu Han ,  Ali Lehaf ,  Steve Cho ,  Thomas Heaton ,  Hiroki Tanaka ,  Kristof Darmawikarta ,  Robert Alan May ,  Sri Ranga Sai Boyapati

IPC: H01L27/082 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.

公开(公告)号：US10790233B2

公开(公告)日：2020-09-29

申请号：US16097597

申请日：2016-05-25

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Kristof Kuwawi Darmawikarta ,  Sri Ranga Sai Boyapati

IPC: H01L21/48 ,  H01L23/538 ,  H01L23/498 ,  H01L23/522 ,  H01L23/525 ,  H01L27/12 ,  H01L49/02 ,  H01L29/786

Abstract: Disclosed herein are package substrates with integrated components, as well as related apparatuses and methods. For example, in some embodiments, an integrated circuit (IC) package, may include: a substrate having opposing first and second faces, an insulating material disposed between the first and second faces, and a thin film transistor (TFT) disposed between the first and second faces, wherein a conductive portion of the TFT is disposed on a layer of the insulating material, and the conductive portion of the TFT is a gate, source, or drain of the TFT; and a die coupled to the first face of the substrate.

公开(公告)号：US10741534B2

公开(公告)日：2020-08-11

申请号：US16145620

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Sri Ranga Sai Boyapati ,  Kristof Darmawikarta ,  Rahul N. Manepalli ,  Robert Alan May ,  Srinivas V. Pietambaram

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/538 ,  H01L23/373

Abstract: The present description addresses example methods for forming multi-chip microelectronic devices and the resulting devices. The multiple semiconductor die of the multichip package will be attached to a solid plate with a bonding system selected to withstand stresses applied when a mold material is applied to encapsulate the die of the multichip device. The solid plate will remain as a portion of the finished multi-chip device. The solid plate can be a metal plate to function as a heat spreader for the completed multi-chip device.

公开(公告)号：US10707168B2

公开(公告)日：2020-07-07

申请号：US16182277

申请日：2018-11-06

Applicant: Intel Corporation

Inventor： Amruthavalli Pallavi Alur ,  Sri Ranga Sai Boyapati ,  Robert Alan May ,  Islam A. Salama ,  Robert L. Sankman

IPC: H01L23/492 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L25/00 ,  H01L25/18 ,  H01L23/31 ,  H01L21/66 ,  H01L21/683 ,  H01L25/11

Abstract: An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.

公开(公告)号：US20200051915A1

公开(公告)日：2020-02-13

申请号：US16474589

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Robert Alan May ,  Sri Ranga Sai Sai Boyapati ,  Wei-Lun Kane Jen ,  Javier Soto Gonzalez

IPC: H01L23/538 ,  H01L23/13 ,  H01L21/48 ,  H01L23/495 ,  H01L21/768 ,  H01L23/532

Abstract: A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect, wherein the bridge die is embedded in the multilayer substrate structure. The die interconnect substrate comprises a via portion formed on the first bridge die pad of the bridge die. An average angle between a surface of the first bridge die pad and a sidewall of the via portion lies between 85° and 95°.

公开(公告)号：US20190250326A1

公开(公告)日：2019-08-15

申请号：US16061540

申请日：2015-12-14

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Kristof Darmawikarta ,  Rahul Jain ,  Sri Ranga Sai Boyapati ,  Maroun Moussallem ,  Rahul N. Manepalli ,  Srinivas Pietambaram

IPC: G02B6/122 ,  G02B6/132 ,  H01P5/107

CPC classification number: G02B6/122 ,  G02B6/132 ,  G02B6/134 ,  G02B2006/12035 ,  H01P5/107

Abstract: This document discusses, among other things, a waveguide including a first metal having an outer surface proximate a dielectric material and an inner surface defining a path of the waveguide, a method of receiving an optical signal at the inner surface of the waveguide and transmitting the optical signal along at least a portion of the path of the waveguide. A method of integrating a waveguide in a substrate includes depositing sacrificial metal on a first surface of a carrier substrate to form a core of the waveguide, depositing a first metal over the sacrificial metal and at least a portion of the first surface of the carrier substrate, forming an outer surface of the waveguide and a conductor separate from the sacrificial metal, and depositing dielectric material over the first surface of the carrier substrate about the conductor.