公开(公告)号：US5594138A

公开(公告)日：1997-01-14

申请号：US453232

申请日：1995-05-30

申请人： Christine C. Dykstra ,  Richard R. Tidwell ,  David W. Boykin ,  W. David Wilson ,  Jaroslaw Spychala ,  Bijan P. Das ,  Arvind Kumar

发明人： Christine C. Dykstra ,  Richard R. Tidwell ,  David W. Boykin ,  W. David Wilson ,  Jaroslaw Spychala ,  Bijan P. Das ,  Arvind Kumar

IPC分类号： G01N33/50 ,  A61K31/505 ,  A61K31/506 ,  C07D307/52 ,  C07D307/54 ,  C07D307/58 ,  C07D403/10 ,  C07D403/14 ,  C07D405/14 ,  C09B23/01 ,  C12Q1/68 ,  G01N21/78 ,  G01N33/52 ,  G01N33/58 ,  C07D405/00

CPC分类号： G01N33/52 ,  A61K31/505 ,  A61K31/506 ,  C07D307/54 ,  C07D403/10 ,  C07D403/14 ,  C07D405/14 ,  C09B23/0075 ,  Y10S435/808 ,  Y10S435/81

摘要： Disclosed is a method of fluorescent detection of a nucleic acid. The method comprises contacting to the nucleic acid a bis-dicationic aryl furan compound, such as 2,5-bis[4-(4,5,6,7-tetrahydro-1H-1,3-diazepin-2-yl) phenyl] furan; 2,5-bis{[4-(N-isopropyl) amidino] phenyl}furan; and physiologically acceptable salts thereof, and exposing the nucleic acid to light at a frequency to induce fluorescence of the compound. A method for fluorescent detection of cytoskeleton elements, and novel bis-dicationic aryl furan compounds are also disclosed.

摘要翻译： 公开了一种荧光检测核酸的方法。 该方法包括使双酸性芳基呋喃化合物如2,5-双[4-（4,5,6,7-四氢-1H-1,3-二氮杂-2-基）苯基 ]呋喃 2,5-双{[4-（N-异丙基）脒基]苯基}呋喃; 和其生理上可接受的盐，并且以一定的频率使核酸暴露以诱导化合物的荧光。 还公开了细胞骨架元件的荧光检测方法，以及新型的双 - 二盐酸芳基呋喃化合物。

公开(公告)号：US09059243B2

公开(公告)日：2015-06-16

申请号：US13531654

申请日：2012-06-25

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

IPC分类号： H01L21/70 ,  H01L21/762

CPC分类号： H01L29/0649 ,  H01L21/76224 ,  H01L21/76283

摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

摘要翻译： 提供了与UTBB（超薄体和掩埋氧化物）半导体衬底一起使用的浅沟槽隔离结构，其防止发生缺陷机制，例如在浅沟槽的侧壁上的硅层的暴露部分之间形成电短路 UTBB衬底，在浅沟槽的沟槽填充材料随后被蚀刻掉并凹入UTBB衬底的上表面的情况下。

公开(公告)号：US08819857B2

公开(公告)日：2014-08-26

申请号：US13404628

申请日：2012-02-24

申请人： Naga Gurumoorthy ,  Arvind Kumar ,  Matthew J. Parker

发明人： Naga Gurumoorthy ,  Arvind Kumar ,  Matthew J. Parker

IPC分类号： G06F11/00

CPC分类号： G06F21/88 ,  G06F9/4401 ,  G06F9/44542 ,  G06F21/575 ,  G06F21/73 ,  G06F2221/2141

摘要： In some embodiments, a processor-based system may include a processor, the processor having a processor identification, one or more electronic components coupled to the processor, at least one of the electronic components having a component identification, and a hardware security component coupled to the processor and the electronic component. The hardware security component may include a secure non-volatile memory and a controller. The controller may be configured to receive the processor identification from the processor, receive the at least one component identification from the one or more electronic components, and determine if a boot of the processor-based system is a provisioning boot of the processor-based system. If the boot is determined to be the provisioning boot, the controller may be configured to store a security code in the secure non-volatile memory, wherein the security code is based on the processor identification and the at least one component identification. Other embodiments are disclosed and claimed.

摘要翻译： 在一些实施例中，基于处理器的系统可以包括处理器，处理器具有处理器标识，耦合到处理器的一个或多个电子部件，具有部件识别的电子部件中的至少一个以及耦合到 处理器和电子元件。 硬件安全组件可以包括安全的非易失性存储器和控制器。 控制器可以被配置为从处理器接收处理器标识，从一个或多个电子部件接收至少一个组件标识，并且确定基于处理器的系统的启动是否是基于处理器的系统的供应引导 。 如果确定引导是供应启动，则控制器可以被配置为将安全代码存储在安全非易失性存储器中，其中安全代码基于处理器标识和至少一个组件标识。 公开和要求保护其他实施例。

公开(公告)号：US20140075211A1

公开(公告)日：2014-03-13

申请号：US13608479

申请日：2012-09-10

申请人： Arvind Kumar ,  Brian E. Woodruff ,  David M. Putzolu ,  Mark R. Walker

发明人： Arvind Kumar ,  Brian E. Woodruff ,  David M. Putzolu ,  Mark R. Walker

IPC分类号： G06F1/26

CPC分类号： G06F1/266 ,  G06F1/3206 ,  G06F1/3234 ,  H04W52/0229 ,  H04W52/0254 ,  Y02D70/164

摘要： A method and system for cascading power consumption is described herein. The method may include providing power to a first sensor and a second sensor, wherein the first sensor consumes more power than the second sensor. The method may also include detecting the first sensor does not capture a sample of data. In addition, the method may include stopping the flow of power to the first sensor. Furthermore, the method may include monitoring an operating environment with the second sensor. The method may also include providing power to the first sensor in response to the second sensor detecting a sample of data.

摘要翻译： 本文描述了用于级联功率消耗的方法和系统。 该方法可以包括向第一传感器和第二传感器提供电力，其中第一传感器比第二传感器消耗更多的功率。 该方法还可以包括检测第一传感器不捕获数据样本。 此外，该方法可以包括停止向第一传感器的电力的流动。 此外，该方法可以包括利用第二传感器来监视操作环境。 该方法还可以包括响应于第二传感器检测数据样本而向第一传感器提供电力。

公开(公告)号：US20130179693A1

公开(公告)日：2013-07-11

申请号：US13782484

申请日：2013-03-01

申请人： Ned M. Smith ,  Vedvyas Shanbhogue ,  Arvind Kumar ,  Purushottam Goel

发明人： Ned M. Smith ,  Vedvyas Shanbhogue ,  Arvind Kumar ,  Purushottam Goel

IPC分类号： G06F21/44

CPC分类号： G06F21/554 ,  G06F21/44 ,  G06F21/57 ,  G06F21/64

摘要： In one embodiment, a processor includes a microcode storage including processor instructions to create and execute a hidden resource manager (HRM) to execute in a hidden environment that is not visible to system software. The processor may further include an extend register to store security information including a measurement of at least one kernel code module of the hidden environment and a status of a verification of the at least one kernel code module. Other embodiments are described and claimed.

公开(公告)号：US08232599B2

公开(公告)日：2012-07-31

申请号：US12683456

申请日：2010-01-07

申请人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

发明人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

IPC分类号： H01L27/12 ,  H01L21/86

CPC分类号： H01L27/1207 ,  H01L21/84

摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.

摘要翻译： 提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度， 与SOI FET的掩埋绝缘层基本共面。 在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。 邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

公开(公告)号：US20120187492A1

公开(公告)日：2012-07-26

申请号：US13425681

申请日：2012-03-21

申请人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

发明人： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

IPC分类号： H01L27/088

CPC分类号： H01L27/1207 ,  H01L21/84

摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.

摘要翻译： 提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度， 与SOI FET的掩埋绝缘层基本共面。 在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。 邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

公开(公告)号：US08132267B2

公开(公告)日：2012-03-06

申请号：US12286352

申请日：2008-09-30

申请人： Naga Gurumoorthy ,  Arvind Kumar ,  Matthew J Parker

发明人： Naga Gurumoorthy ,  Arvind Kumar ,  Matthew J Parker

IPC分类号： G06F11/00

CPC分类号： G06F21/88 ,  G06F9/4401 ,  G06F9/44542 ,  G06F21/575 ,  G06F21/73 ,  G06F2221/2141

摘要： In some embodiments, a processor-based system may include a processor, the processor having a processor identification, one or more electronic components coupled to the processor, at least one of the electronic components having a component identification, and a hardware security component coupled to the processor and the electronic component. The hardware security component may include a secure non-volatile memory and a controller. The controller may be configured to receive the processor identification from the processor, receive the at least one component identification from the one or more electronic components, and determine if a boot of the processor-based system is a provisioning boot of the processor-based system. If the boot is determined to be the provisioning boot, the controller may be configured to store a security code in the secure non-volatile memory, wherein the security code is based on the processor identification and the at least one component identification. Other embodiments are disclosed and claimed.

摘要翻译： 在一些实施例中，基于处理器的系统可以包括处理器，处理器具有处理器标识，耦合到处理器的一个或多个电子部件，具有部件识别的电子部件中的至少一个以及耦合到 处理器和电子元件。 硬件安全组件可以包括安全的非易失性存储器和控制器。 控制器可以被配置为从处理器接收处理器标识，从一个或多个电子部件接收至少一个组件标识，并且确定基于处理器的系统的启动是否是基于处理器的系统的供应引导 。 如果确定引导是供应启动，则控制器可以被配置为将安全代码存储在安全非易失性存储器中，其中安全代码基于处理器标识和至少一个组件标识。 公开和要求保护其他实施例。

公开(公告)号：US20110145598A1

公开(公告)日：2011-06-16

申请号：US12639616

申请日：2009-12-16

申请人： Ned M. Smith ,  Vedvyas Shanbhogue ,  Arvind Kumar ,  Purushottam Goel

发明人： Ned M. Smith ,  Vedvyas Shanbhogue ,  Arvind Kumar ,  Purushottam Goel

IPC分类号： G06F9/30 ,  G06F21/22 ,  G06F9/02 ,  G06F15/76 ,  G06F1/32

CPC分类号： G06F21/554 ,  G06F21/44 ,  G06F21/57 ,  G06F21/64

摘要： In one embodiment, a processor includes a microcode storage including processor instructions to create and execute a hidden resource manager (HRM) to execute in a hidden environment that is not visible to system software. The processor may further include an extend register to store security information including a measurement of at least one kernel code module of the hidden environment and a status of a verification of the at least one kernel code module. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括微代码存储器，其包括处理器指令，用于创建和执行在系统软件不可见的隐藏环境中执行的隐藏资源管理器（HRM）。 处理器还可以包括扩展寄存器，用于存储包括隐藏环境的至少一个内核代码模块的测量值和至少一个内核代码模块的验证状态的安全信息。 描述和要求保护其他实施例。

公开(公告)号：US20110089499A1

公开(公告)日：2011-04-21

申请号：US12581924

申请日：2009-10-20

申请人： Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert R. Robison

发明人： Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert R. Robison

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/26586 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66659

摘要： A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.