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69 条记录 (耗时 0.028 秒)

    Programmable delay for clock phase error correction
    61.
    发明授权
    Programmable delay for clock phase error correction 失效
    时钟相位误差校正的可编程延迟

    公开(公告)号：US07545194B2

    公开(公告)日：2009-06-09

    申请号：US11479520

    申请日：2006-06-30

    申请人： Suwei Chen ,  Aaron K. Martin ,  Ying L. Zhou

    发明人： Suwei Chen ,  Aaron K. Martin ,  Ying L. Zhou

    IPC分类号： H03H11/26

    CPC分类号： H03K5/13 ,  H03K2005/00052 ,  H03K2005/00071 ,  H04L7/0008

    摘要： A method, circuit, and system are disclosed. In one embodiment, the method comprises receiving a differential clock signal from two clock signal lines into a first differential pair of transistors of a first size, receiving the differential clock signal from the two clock signal lines into a second differential pair of transistors of a size smaller than the first size, converting the differential clock signal into a single-ended clock signal, outputting the single-ended clock signal through an inverter, and synchronizing any differential clock phase error by controlling the transconductance between the first differential pair of transistors and the second differential pair of transistors.

    摘要翻译： 公开了一种方法，电路和系统。 在一个实施例中，该方法包括：将来自两个时钟信号线的差分时钟信号接收到第一尺寸的第一差分晶体管中，从两个时钟信号线接收差分时钟信号，以形成尺寸为 小于第一尺寸，将差分时钟信号转换为单端时钟信号，通过反相器输出单端时钟信号，并通过控制第一差分晶体管与第一差分对晶体管之间的跨导来同步任何差分时钟相位误差 第二差分晶体管对。

    Circuit to syncrhonize the phase of a distributed clock signal with a received clock signal
    64.
    发明申请
    Circuit to syncrhonize the phase of a distributed clock signal with a received clock signal 有权
    电路用接收到的时钟信号使分布式时钟信号的相位同步

    公开(公告)号：US20080049883A1

    公开(公告)日：2008-02-28

    申请号：US11510959

    申请日：2006-08-28

    申请人： Taner Sumesaglam ,  Aaron K. Martin

    发明人： Taner Sumesaglam ,  Aaron K. Martin

    IPC分类号： H04L7/04

    CPC分类号： H04L7/0025

    摘要： A circuit to synchronize the phase of a distributed clock signal to a received clock signal. Embodiments include a control loop comprising a phase interpolator, a clock distribution network, and a data receiver. The clock distribution network provides a sampling clock signal to clock the data receiver. The data receiver receives as its input the received clock signal. Control logic maps a subset of the output samples to a value, and this value is added to the phase introduced by the phase interpolator to provide an updated phase. Embodiments include a second phase interpolator and a second distribution network to clock a second data receiver, where the second data receiver receives the data. The control logic adjusts the second phase interpolator in the same way that it adjusts the phase interpolator. The two data receivers are matched to each other, and the two clock distribution networks are matched to each other. Other embodiments are described and claimed.

    摘要翻译： 分配时钟信号的相位与所接收的时钟信号同步的电路。 实施例包括包括相位内插器，时钟分配网络和数据接收器的控制回路。 时钟分配网络提供采样时钟信号来对数据接收器进行时钟。 数据接收器接收接收到的时钟信号作为其输入。 控制逻辑将输出采样的子集映射到一个值，并将该值添加到由相位插值器引入的相位以提供更新的相位。 实施例包括第二相位内插器和第二分配网络，用于对第二数据接收器进行计时，其中第二数据接收器接收数据。 控制逻辑以与调整相位内插器相同的方式调节第二相位内插器。 两个数据接收器彼此匹配，并且两个时钟分配网络彼此匹配。 描述和要求保护其他实施例。

    Using a timing strobe for synchronization and validation in a digital logic device
    67.
    发明授权
    Using a timing strobe for synchronization and validation in a digital logic device 有权
    在数字逻辑器件中使用定时选通器进行同步和验证

    公开(公告)号：US06437601B1

    公开(公告)日：2002-08-20

    申请号：US09752906

    申请日：2000-12-26

    申请人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    发明人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    IPC分类号： H03K19096

    CPC分类号： G11C7/222 ,  G11C7/22 ,  H03L7/00 ,  H03L7/0812 ,  H04L7/0008

    摘要： In an electronic system having first and second logic devices, a free running on-chip clock signal is generated by the first logic device, where the signal has a frequency that is controlled to match that of a global free-running clock signal received by both devices. The on-chip clock signal is synchronized to a strobe signal received by the first device and that was transmitted in association with a data signal by the second device. A logic function is repeatedly performed as synchronized by the first clock signal, to repeatedly generate one or more bits from the data signal.

    摘要翻译： 在具有第一和第二逻辑器件的电子系统中，由第一逻辑器件产生自由运行的片上时钟信号，其中信号的频率被控制以匹配由两者接收的全局自由运行时钟信号的频率 设备。 片上时钟信号与第一器件接收的选通信号同步，并与第二器件与数据信号相关联地发送。 重复执行由第一时钟信号同步的逻辑功能，以从数据信号重复产生一个或多个位。

    Data and strobe repeater having a frequency control unit to re-time the data and reject delay variation in the strobe
    68.
    发明授权
    Data and strobe repeater having a frequency control unit to re-time the data and reject delay variation in the strobe 有权
    具有频率控制单元的数据和选通中继器，用于对数据进行重新计时并拒绝选通脉冲的延迟变化

    公开(公告)号：US06373289B1

    公开(公告)日：2002-04-16

    申请号：US09752895

    申请日：2000-12-26

    申请人： Aaron K. Martin ,  Stephen R. Mooney ,  Joseph T. Kennedy ,  Matthew B. Haycock ,  Shekhar Y. Borkar

    发明人： Aaron K. Martin ,  Stephen R. Mooney ,  Joseph T. Kennedy ,  Matthew B. Haycock ,  Shekhar Y. Borkar

    IPC分类号： H03K1900

    CPC分类号： H03L7/0812 ,  H03K5/135 ,  H04L25/242

    摘要： A frequency control unit has an input to receive a digital downstream strobe signal and an output to provide a controlled delay to the input strobe signal. A downstream latch has a data input to receive a digital downstream data signal and a clock input coupled to the output of the frequency control unit. The controlled delay is essentially equal to a set up time of the latch. A delay element coupled to the output of the frequency control unit further delays the downstream strobe signal by essentially a propagation time of the latch. Output drivers are coupled to the outputs of the latch and the delay element.

    摘要翻译： 频率控制单元具有用于接收数字下行选通信号和输出的输入，以向输入选通信号提供受控的延迟。 下游锁存器具有用于接收数字下行数据信号的数据输入和耦合到频率控制单元的输出的时钟输入。 受控延迟基本上等于锁存器的设定时间。 耦合到频率控制单元的输出的延迟元件进一步延迟下游选通信号基本上是锁存器的传播时间。 输出驱动器耦合到锁存器和延迟元件的输出。