公开(公告)号：US20130065380A1

公开(公告)日：2013-03-14

申请号：US13350523

申请日：2012-01-13

申请人： Victor Moroz ,  Lars Bomholt

发明人： Victor Moroz ,  Lars Bomholt

IPC分类号： H01L21/20 ,  H01L21/302

CPC分类号： H01L29/045 ,  G06F17/5045 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/0676

摘要： A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line. The straightened sidewall surface does not carry the sidewall surface variations introduced by photolithographic processes, or other patterning processes, involved in forming the mask element and etching the line.

摘要翻译： 描述了一种诸如集成电路器件的结构，其包括具有临界尺寸的材料线，其在基本上小于在蚀刻线中使用的掩模元件（例如图案化的抗蚀剂元件）的分布内变化。 描述了用于处理已经使用掩模元件蚀刻的一系列晶相材料的技术，其以直线化该线的蚀刻侧壁表面的方式。 拉直的侧壁表面不承载由形成掩模元件并蚀刻线的光刻工艺或其它图案化工艺引入的侧壁表面变化。

公开(公告)号：US20130026607A1

公开(公告)日：2013-01-31

申请号：US13190319

申请日：2011-07-25

申请人： Victor Moroz ,  Lars Bomholt

发明人： Victor Moroz ,  Lars Bomholt

IPC分类号： H01L29/04 ,  H01L21/425

CPC分类号： H01L29/045 ,  H01L21/26506 ,  H01L21/30604 ,  H01L29/04 ,  H01L29/66795

摘要： A structure such as an integrated circuit device is described having a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in manufacturing the line of material.

公开(公告)号：US08362622B2

公开(公告)日：2013-01-29

申请号：US12430008

申请日：2009-04-24

申请人： James David Sproch ,  Victor Moroz ,  Xiaopeng Xu ,  Aditya Pradeep Karmarkar

发明人： James David Sproch ,  Victor Moroz ,  Xiaopeng Xu ,  Aditya Pradeep Karmarkar

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： G06F17/5072 ,  G06F17/5009 ,  G06F17/5036 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  G06F2217/82 ,  H01L21/76898 ,  H01L21/823807 ,  H01L27/0207 ,  H01L29/7845 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

摘要： Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.

摘要翻译： 粗略地描述，本发明涉及表征，考虑或利用TSV近晶体管引入的应力的方法。 在表征电路时，可以考虑TSV和附近晶体管之间的物理关系。 在不了解TSV和附近晶体管之间的物理关系的情况下导出的布局可以进行修改。 宏单元可以包括TSV和附近晶体管，以及考虑到晶体管和TSV之间的物理关系的宏单元的仿真模型。 宏单元可以包括TSV和附近的晶体管，其中一个晶体管相对于其他晶体管旋转。 IC还可以包括在TSV附近的晶体管，以将通道中的载流子迁移率改变超过先前认为限定禁区的极限。

公开(公告)号：US08349668B2

公开(公告)日：2013-01-08

申请号：US13103677

申请日：2011-05-09

申请人： Victor Moroz ,  Tsu-Jae King Liu

发明人： Victor Moroz ,  Tsu-Jae King Liu

IPC分类号： H01L21/20

CPC分类号： H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/7843

摘要： Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientation and a single strained capping layer can be used for both n-channel FinFETs (nFinFETs) and p-channel FinFETs (pFinFETs). In another approach including more process steps (thereby increasing manufacturing cost) but providing a significantly higher performance boost, different surface/channel direction orientations and different strained capping layers can be used for nFinFETs and pFinFETs.

摘要翻译： 提供了基于表面/通道方向和应变封盖层类型的FinFET性能增强的不同方法。 在提供性能提升的一种相对简单和便宜的方法中，可以将n沟道FinFET（nFinFET）和p沟道FinFET（pFinFET）用于单个表面/沟道方向取向和单个应变封装层。 在包括更多工艺步骤（从而增加制造成本）但提供显着更高性能提升的另一种方法中，不同的表面/沟道方向取向和不同的应变封装层可用于nFinFET和pFinFET。

公开(公告)号：US08347252B2

公开(公告)日：2013-01-01

申请号：US12510938

申请日：2009-07-28

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： G06F17/50

CPC分类号： H01L21/823412 ,  G06F17/5036 ,  H01L21/823425 ,  H01L27/0207

摘要： An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si/STI edges on the selected area as well as channel areas and their associated gate/Si edges. Next, the threshold voltage variations in each identified channel area are identified, which requires further steps of calculating threshold voltage variations due to effects in a longitudinal direction; calculating threshold voltage variations due to effects in a transverse direction; and combining the longitudinal and transverse variations to provide an overall variation. Finally, a total variation is determined by combining variations from individual channel variations.

公开(公告)号：US20110309453A1

公开(公告)日：2011-12-22

申请号：US13221747

申请日：2011-08-30

申请人： Victor Moroz ,  Dipankar Pramanik ,  Xi-Wei Lin

发明人： Victor Moroz ,  Dipankar Pramanik ,  Xi-Wei Lin

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L29/7846

摘要： Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel diffusions are not suppressed; preferably they have an elevation that is at least as high as that of the diffusion regions.

摘要翻译： 粗略描述，晶体管沟道区域在某些相邻STI区域的水平上升高。 优选地，与扩散区横向相邻的STI区域被抑制，与N沟道扩散区域纵向相邻的STI区也是如此。 优选地，与P沟道扩散纵向相邻的STI区域不被抑制; 优选地，它们具有至少与扩散区域相同的高度。

公开(公告)号：US07968413B2

公开(公告)日：2011-06-28

申请号：US12176274

申请日：2008-07-18

申请人： Faran Nouri ,  Lori D. Washington ,  Victor Moroz

发明人： Faran Nouri ,  Lori D. Washington ,  Victor Moroz

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

摘要： Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon-germanium material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon-germanium material to form a source/drain region having a second conductivity.

摘要翻译： 提供了用于在诸如金属氧化物晶体管的衬底上形成半导体器件中沉积材料的方法。 在一个实施例中，本发明通常提供一种处理衬底的方法，包括在具有第一导电性的衬底上形成栅极电介质，在栅极电介质上形成栅电极，在栅极的横向相对的侧壁上形成第一对侧壁间隔物 在电极的相对侧蚀刻一对源/漏区定义，在源/漏区定义中选择性地沉积硅 - 锗材料，以及在沉积的硅 - 锗材料中注入掺杂剂以形成源极/漏极 区域具有第二导电性。

公开(公告)号：US07681164B2

公开(公告)日：2010-03-16

申请号：US11848524

申请日：2007-08-31

申请人： Xi-Wei Lin ,  Victor Moroz

发明人： Xi-Wei Lin ,  Victor Moroz

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A system that places an integrated circuit (IC) device within an IC chip layout is presented. During operation, the system receives the IC device to be placed within the IC chip layout, wherein the IC chip layout includes one or more continuous rows of diffusion. Next, the system places the IC device within a continuous row of diffusion. The system then determines whether the IC device is to be electrically isolated from other IC devices. If so, the system inserts one or more isolation devices within the continuous row of diffusion so that the IC device can be electrically isolated from other IC devices. The system then biases the one or more isolation device so that the IC device is electrically isolated from other IC devices within the continuous row of diffusion.

摘要翻译： 提出了一种将集成电路（IC）器件放置在IC芯片布局内的系统。 在操作期间，系统接收要放置在IC芯片布局内的IC器件，其中IC芯片布局包括一个或多个连续的扩散行。 接下来，系统将IC器件放置在连续的扩散行内。 然后，系统确定IC器件是否与其他IC器件电隔离。 如果是这样，系统将一个或多个隔离装置插入连续的扩散行内，使得IC器件可以与其它IC器件电隔离。 然后，该系统偏置一个或多个隔离装置，使得IC器件与连续的扩散排中的其它IC器件电隔离。

公开(公告)号：US20100042958A1

公开(公告)日：2010-02-18

申请号：US12582453

申请日：2009-10-20

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5022 ,  G06F17/5081

摘要： Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

公开(公告)号：US20090288048A1

公开(公告)日：2009-11-19

申请号：US12510187

申请日：2009-07-27

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5022 ,  G06F17/5081

摘要： Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

摘要翻译： 粗略地描述了一种用于近似集成电路布局中的沟道区域中的应力诱导迁移率增强的方法，包括近似在通道中的多个采样点中的每一个处的应力，将每个采样点处的应力近似转换为 相应的移动性增强值，并在所有采样点平均移动性增强值。 该方法实现了集成电路应力分析，其考虑了由多个应力产生机制所产生的应力，具有沿通道长度以外的矢量分量的应力，以及由于在邻域中存在其它结构的应力贡献（包括缓解） 正在研究的频道区域，除了最接近的STI接口。 该方法还能够对大型布局区域甚至全芯片布局进行应力分析，而不会导致完整TCAD仿真的计算成本。