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    Enhanced segmented channel MOS transistor with narrowed base regions
    2.
    发明授权
    Enhanced segmented channel MOS transistor with narrowed base regions 有权
    具有窄基极区域的增强型分段沟道MOS晶体管

    公开(公告)号：US07508031B2

    公开(公告)日：2009-03-24

    申请号：US11668756

    申请日：2007-01-30

    申请人： Tsu Jae King Liu ,  Qiang Lu

    发明人： Tsu Jae King Liu ,  Qiang Lu

    IPC分类号： H01L21/336

    CPC分类号： H01L27/0207 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/785

    摘要： By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably produced. Ridges on the corrugated substrate can be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping, “wrapped” gates, epitaxially grown conductive regions, epitaxially grown high mobility semiconductor materials, high-permittivity ridge isolation material, and narrowed base regions can be used in conjunction with the segmented channel regions to further enhance device performance.

    摘要翻译： 通过在具有预先存在的半导体材料脊（即，“波纹状基板”）的基板上形成MOSFET，可以克服与常规半导体制造工艺相关的分辨率限制，并且可以可靠地生产高性能的低功率晶体管 。 可以使用通常不适合于设备生产的高精度技术来创建瓦楞纸板上的脊。 随后将高精度脊结合到其沟道区中的MOSFET通常将显示出比使用不能提供相同程度的图案精度的基于光刻技术形成的类似的MOSFET更精确和更少可变的性能。 附加的性能增强技术，例如脉冲形掺杂，“包裹”栅极，外延生长的导电区域，外延生长的高迁移率半导体材料，高电容率脊隔离材料和窄基极区域可以与分段的沟道区域结合使用 进一步提升设备性能。

    Method for achieving uniform etch depth using ion implantation and a timed etch
    3.
    发明授权
    Method for achieving uniform etch depth using ion implantation and a timed etch 有权
    使用离子注入和定时蚀刻实现均匀蚀刻深度的方法

    公开(公告)号：US07494933B2

    公开(公告)日：2009-02-24

    申请号：US11424826

    申请日：2006-06-16

    申请人： Tsu-Jae King Liu

    发明人： Tsu-Jae King Liu

    IPC分类号： H01L21/302

    CPC分类号： H01L29/0653 ,  H01L21/26506 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/76224 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853

    摘要： A method of performing a timed etch of a material to a precise depth is provided. In this method, ion implantation of the material is performed before the timed etch. This ion implantation process substantially enhances the etch rate of the material within a precisely controlled depth range corresponding to the range of implantation-induced damage. By using the ion implantation, the variation in vertical etch depth can be reduced by a factor approximately equal to the etch rate of the damaged material divided by the etch rate of the undamaged material. The vertical etch depth can be used to provide a vertical dimension of a non-planar semiconductor device. Minimizing vertical device dimension variations on a wafer can reduce device and circuit performance variations, which is highly desirable.

    摘要翻译： 提供了将材料定时蚀刻到精确深度的方法。 在该方法中，在定时蚀刻之前进行材料的离子注入。 该离子注入工艺基本上增强了对应于植入引起的损伤范围的精确控制的深度范围内的材料的蚀刻速率。 通过使用离子注入，可以将垂直蚀刻深度的变化减小大约等于受损材料的蚀刻速率除以未损坏材料的蚀刻速率的因子。 垂直蚀刻深度可用于提供非平面半导体器件的垂直尺寸。 最小化晶片上的垂直器件尺寸变化可以减少器件和电路性能变化，这是非常需要的。

    Patterning A Single Integrated Circuit Layer Using Multiple Masks And Multiple Masking Layers
    5.
    发明申请
    Patterning A Single Integrated Circuit Layer Using Multiple Masks And Multiple Masking Layers 有权
    使用多个掩码和多个掩蔽层对单个集成电路层进行图案化

    公开(公告)号：US20080280217A1

    公开(公告)日：2008-11-13

    申请号：US12178472

    申请日：2008-07-23

    申请人： Tsu-Jae King Liu

    发明人： Tsu-Jae King Liu

    IPC分类号： G03F7/20 ,  G03F1/00 ,  G03B27/42

    CPC分类号： H01L21/0337 ,  G03F1/70 ,  G03F7/70466 ,  H01L21/033

    摘要： A multiple mask and a multiple masking layer technique can be used to pattern a single IC layer. A resolution enhancement technique can be used to define one or more fine-line patterns in a first masking layer, wherein each fine-line feature is sub-wavelength. Moreover, the pitch of each fine-line pattern is less than or equal to that wavelength. The portions of the fine-line features not needed to implement the circuit design are then removed or designated for removal using a mask. After patterning of the first masking layer, another mask can then be used to define coarse features in a second masking layer formed over the patterned first masking layer. At least one coarse feature is defined to connect two fine-line features, wherein the coarse feature(s) can be derived from a desired layout using a shrink/grow operation. The IC layer can be patterned using the composite mask formed by the patterned first and second masking layers.

    摘要翻译： 可以使用多重掩模和多重掩模层技术来对单个IC层进行图案化。 可以使用分辨率增强技术来定义第一掩模层中的一个或多个细线图案，其中每个细线特征是亚波长。 此外，每个细线图案的间距小于或等于该波长。 然后，不需要实现电路设计的细线特征的部分被移除或指定为使用掩模去除。 在图案化第一掩模层之后，可以使用另一个掩模来在图案化的第一掩蔽层上形成的第二掩模层中定义粗糙特征。 定义至少一个粗糙特征以连接两个细线特征，其中粗糙特征可以使用收缩/增长操作从期望的布局导出。 可以使用由图案化的第一和第二掩模层形成的复合掩模来图案化IC层。

    Patterning a single integrated circuit layer using automatically-generated masks and multiple masking layers
    7.
    发明授权
    Patterning a single integrated circuit layer using automatically-generated masks and multiple masking layers 有权

    公开(公告)号：US08399183B2

    公开(公告)日：2013-03-19

    申请号：US12465562

    申请日：2009-05-13

    申请人： Tsu-Jae King Liu

    发明人： Tsu-Jae King Liu

    IPC分类号： G03F7/20

    CPC分类号： G03F1/00 ,  G03F1/36 ,  G03F1/70 ,  G03F7/70466

    摘要： A multiple mask and a multiple masking layer technique can be used to pattern an IC layer. A RET can be used to define one or more fine-line patterns in a first masking layer. Portions of the fine-line features are then removed or designated for removal using a mask. This removal/designation can include accessing a desired layout (with at least one layout feature including a fine-line feature and a coarse feature) and expanding layout features only in directions along critical dimensions of those layout features. Another mask can then be used to define coarse features in a second masking layer formed over the patterned first masking layer. Coarse feature(s) can be derived from the desired layout using a shrink/grow operation performed only in directions orthogonal to a critical dimension of the fine-line features. The IC layer can be patterned using the composite mask formed by the patterned first and second masking layers.

    Patterning a single integrated circuit layer using multiple masks and multiple masking layers
    8.
    发明授权
    Patterning a single integrated circuit layer using multiple masks and multiple masking layers 有权
    使用多个掩模和多个屏蔽层对单个集成电路层进行图案化

    公开(公告)号：US07537866B2

    公开(公告)日：2009-05-26

    申请号：US11420217

    申请日：2006-05-24

    申请人： Tsu-Jae King Liu

    发明人： Tsu-Jae King Liu

    IPC分类号： G03F9/00 ,  G03C5/00

    CPC分类号： G03F7/70466 ,  G03F1/70 ,  H01L21/0337

    摘要： A multiple mask and a multiple masking layer technique can be used to pattern a single IC layer. A resolution enhancement technique can be used to define one or more fine-line patterns in a first masking layer, wherein each fine-line feature is sub-wavelength. Moreover, the pitch of each fine-line pattern is less than or equal to that wavelength. The portions of the fine-line features not needed to implement the circuit design are then removed or designated for removal using a mask. After patterning of the first masking layer, another mask can then be used to define coarse features in a second masking layer formed over the patterned first masking layer. At least one coarse feature is defined to connect two fine-line features. The IC layer can be patterned using the composite mask formed by the patterned first and second masking layers.

    摘要翻译： 可以使用多重掩模和多重掩模层技术来对单个IC层进行图案化。 可以使用分辨率增强技术来定义第一掩模层中的一个或多个细线图案，其中每个细线特征是亚波长。 此外，每个细线图案的间距小于或等于该波长。 然后，不需要实现电路设计的细线特征的部分被移除或指定为使用掩模去除。 在图案化第一掩模层之后，可以使用另一个掩模来在图案化的第一掩蔽层上形成的第二掩模层中限定粗糙特征。 定义至少一个粗糙特征来连接两条细线特征。 可以使用由图案化的第一和第二掩模层形成的复合掩模来图案化IC层。

    Method For Achieving Uniform Etch Depth Using Ion Implantation And A Timed Etch
    9.
    发明申请
    Method For Achieving Uniform Etch Depth Using Ion Implantation And A Timed Etch 审中-公开
    使用离子注入和定时蚀刻实现均匀蚀刻深度的方法

    公开(公告)号：US20090114953A1

    公开(公告)日：2009-05-07

    申请号：US12352475

    申请日：2009-01-12

    申请人： Tsu-Jae King Liu

    发明人： Tsu-Jae King Liu

    IPC分类号： H01L29/06 ,  H01L29/772 ,  H01L29/92

    CPC分类号： H01L29/0653 ,  H01L21/26506 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/76224 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853

    摘要： A method of performing a timed etch of a material to a precise depth is provided. In this method, ion implantation of the material is performed before the timed etch. This ion implantation process substantially enhances the etch rate of the material within a precisely controlled depth range corresponding to the range of implantation-induced damage. By using the ion implantation, the variation in vertical etch depth can be reduced by a factor approximately equal to the etch rate of the damaged material divided by the etch rate of the undamaged material. The vertical etch depth can be used to provide a vertical dimension of a non-planar semiconductor device. Minimizing vertical device dimension variations on a wafer can reduce device and circuit performance variations, which is highly desirable.

    摘要翻译： 提供了将材料定时蚀刻到精确深度的方法。 在该方法中，在定时蚀刻之前进行材料的离子注入。 该离子注入工艺基本上增强了对应于植入引起的损伤范围的精确控制的深度范围内的材料的蚀刻速率。 通过使用离子注入，可以将垂直蚀刻深度的变化减小大约等于受损材料的蚀刻速率除以未损坏材料的蚀刻速率的因子。 垂直蚀刻深度可用于提供非平面半导体器件的垂直尺寸。 最小化晶片上的垂直器件尺寸变化可以减少器件和电路性能变化，这是非常需要的。

    Electro-Mechanical Diode Non-Volatile Memory Cell For Cross-Point Memory Arrays
    10.
    发明申请
    Electro-Mechanical Diode Non-Volatile Memory Cell For Cross-Point Memory Arrays 有权
    用于交叉点存储器阵列的机电二极管非易失性存储单元

    公开(公告)号：US20150016185A1

    公开(公告)日：2015-01-15

    申请号：US14241379

    申请日：2012-09-12

    申请人： Tsu-Jae King Liu ,  Wookhyun Kwon

    发明人： Tsu-Jae King Liu ,  Wookhyun Kwon

    IPC分类号： G11C11/38

    CPC分类号： G11C11/38 ,  G11C11/36 ,  G11C11/50 ,  H01L27/1021

    摘要： A non-volatile electro-mechanical diode memory cell is described for implementation of compact (4F2) cross-point memory arrays. The electro-mechanical diode memory cells operate with relatively low set/reset voltages and excellent retention characteristics, and are multi-time programmable. Due to its simplicity, this electro-mechanical diode memory cell is attractive for implementation of three-dimensional memory arrays for higher storage density.

    摘要翻译： 描述了用于实现紧凑（4F2）交叉点存储器阵列的非易失性机电二极管存储器单元。 机电二极管存储单元以相对低的设定/复位电压和优异的保持特性工作，并且是多时间可编程的。 由于其简单性，该机电二极管存储单元对于实现用于更高存储密度的三维存储器阵列是有吸引力的。