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112 条记录 (耗时 0.029 秒)

    Virtual wire signaling
    63.
    发明授权
    Virtual wire signaling 失效
    虚拟线路信令

    公开(公告)号：US07039047B1

    公开(公告)日：2006-05-02

    申请号：US09433654

    申请日：1999-11-03

    申请人： Jasmin Ajanovic ,  David Harriman

    发明人： Jasmin Ajanovic ,  David Harriman

    IPC分类号： H04L12/56

    CPC分类号： G06F13/4022

    摘要： A method and apparatus for implementing virtual wire signaling is described. It includes an apparatus including a first component, a bus coupled to the first component, the bus to transmit packets of data, and a second component coupled to the bus, messages passed between the first component and the second component through packets transmitted on the bus.

    摘要翻译： 描述了用于实现虚拟线路信令的方法和装置。 它包括一种装置，包括第一部件，耦合到第一部件的总线，用于传输数据分组的总线，以及耦合到总线的第二部件，通过在总线上发送的分组在第一部件和第二部件之间传递的消息 。

    Memory controller with a plurality of memory address buses
    64.
    发明授权
    Memory controller with a plurality of memory address buses 失效
    具有多个存储器地址总线的存储器控​​制器

    公开(公告)号：US06260105B1

    公开(公告)日：2001-07-10

    申请号：US08954620

    申请日：1997-10-20

    申请人： Mike W. Williams ,  Jasmin Ajanovic ,  Joseph H. Salmon

    发明人： Mike W. Williams ,  Jasmin Ajanovic ,  Joseph H. Salmon

    IPC分类号： G06F1206

    CPC分类号： G06F13/1684 ,  Y02D10/14

    摘要： A memory controller for a computer system includes a first memory address bus and a second memory, address bus. The memory controller further includes circuitry that toggles one of the first and second memory address buses at a time. Because only one memory address bus is toggled at once, the first and second memory address buses can share power and ground pins, thereby reducing the number of power and ground pins on the memory controller.

    摘要翻译： 用于计算机系统的存储器控​​制器包括第一存储器地址总线和第二存储器地址总线。 存储器控制器还包括一次切换第一和第二存储器地址总线之一的电路。 因为一次只切换一个存储器地址总线，所以第一和第二存储器地址总线可以共享电源和接地引脚，从而减少存储器控制器上的电源和接地引脚的数量。

    Method and apparatus for selectively receiving write data within a write buffer of a host bridge
    65.
    发明授权
    Method and apparatus for selectively receiving write data within a write buffer of a host bridge 失效
    用于在主桥的写缓冲器内选择性地接收写数据的方法和装置

    公开(公告)号：US5758166A

    公开(公告)日：1998-05-26

    申请号：US650166

    申请日：1996-05-20

    申请人： Jasmin Ajanovic

    发明人： Jasmin Ajanovic

    IPC分类号： G06F13/40 ,  G06F13/362

    CPC分类号： G06F13/4059

    摘要： A computer system including amongst its components a host bus coupled to a processor, an intermediate (PCI) bus, an expansion (ISA or EISA) bus, a host bridge coupled between the host and intermediate busses, and an expansion bridge coupled between the intermediate and expansion busses, is disclosed. The host bridge incorporates data buffer management circuitry which examines a write request presented to the host bridge to determine whether the write request is to a device not coupled to the expansion bus. If the write request is to a device not coupled to the expansion bridge, the buffer management allows the write buffer to accept write data associated within the write request. If not, the buffer management circuitry prevents the write buffer from accepting the write data associated with the write request. The data buffer management circuitry may be configured to determine specifically whether the write request is to a graphics frame buffer.

    摘要翻译： 一种计算机系统，包括耦合到处理器的主机总线，中间（PCI）总线，扩展（ISA或EISA）总线，耦合在主机和中间总线之间的主桥，以及耦合在中间 和扩展总线，被披露。 主桥结合了数据缓冲器管理电路，其检查呈现给主机桥的写请求，以确定写请求是否是未耦合到扩展总线的设备。 如果写入请求是未连接到扩展桥的器件，则缓冲器管理允许写入缓冲器接受与写入请求相关联的写入数据。 如果不是，则缓冲器管理电路防止写入缓冲器接受与写入请求相关联的写入数据。 数据缓冲器管理电路可以被配置为具体地确定写入请求是否是对图形帧缓冲器。

    Computer card insertion detection circuit
    66.
    发明授权
    Computer card insertion detection circuit 失效
    电脑卡插入检测电路

    公开(公告)号：US5636347A

    公开(公告)日：1997-06-03

    申请号：US733335

    申请日：1996-10-17

    申请人： Michael J. Muchnick ,  Jerry A. Verseput ,  Jasmin Ajanovic

    发明人： Michael J. Muchnick ,  Jerry A. Verseput ,  Jasmin Ajanovic

    IPC分类号： G06F13/40 ,  G06K7/00 ,  H05K1/11 ,  G06F13/20

    CPC分类号： H05K1/117 ,  G06F13/4072 ,  G06K7/0047 ,  H05K2201/0746 ,  H05K2201/094 ,  H05K2201/10022

    摘要： A personal computer (PC) card insertion method and apparatus uses a subset of connector ground terminals and pins, located at either end of the connector, for detecting the onset of a card insertion. The host PC card slot connector has pull-up resistors for keeping the subset of ground terminals at a high logic level (V.sub.CC). Also, the subset of pins are made longer than the signal pins so that when an insertion of a PC card begins, the grounding of one or more of the subset of pins indicates that a PC card insertion has begun, allowing the host system to take the necessary precautions to ensure an orderly acceptance of the card without any undesirable system affects that might otherwise result. Also, a logic network for using the subset of connector terminals as additional grounding connections is provided upon completion of the insertion.

    摘要翻译： 个人计算机（PC）卡插入方法和装置使用位于连接器两端的连接器接地端子和引脚的子集，用于检测卡插入的开始。 主机PC卡插槽连接器具有用于将接地端子子集保持在高逻辑电平（VCC）的上拉电阻。 此外，引脚的子集比信号引脚长，使得当PC卡的插入开始时，引脚子集中的一个或多个的接地表示PC卡插入已经开始，允许主机系统采取 必要的预防措施，以确保有序地接受卡而没有任何不期望的系统可能会导致的影响。 此外，在插入完成时提供用于使用连接器端子子集作为附加接地连接的逻辑网络。