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公开(公告)号：US08283202B2
公开(公告)日：2012-10-09
申请号：US12549997
申请日：2009-08-28
IPC分类号： H01L45/00
CPC分类号： H01L45/148 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/1683
摘要： A method of fabricating a phase change memory element within a semiconductor structure includes etching an opening to an upper surface of a bottom electrode, the opening being formed of a height equal to a height of a metal region at a same layer within the semiconductor structure, depositing phase change material within the opening, recessing the phase change material within the opening, and forming a top electrode on the recessed phase change material.
摘要翻译： 在半导体结构内制造相变存储元件的方法包括蚀刻到底部电极的上表面的开口，该开口由等于半导体结构内同一层的金属区域的高度的高度形成， 在开口内沉积相变材料，使开关内的相变材料凹陷，并在凹陷相变材料上形成顶部电极。
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62.发明授权Method to tailor location of peak electric field directly underneath an extension spacer for enhanced programmability of a prompt-shift device 有权方法可以直接在扩展垫片下方定制峰值电场的位置，以提高快速移位装置的可编程性公开(公告)号：US08278197B2
公开(公告)日：2012-10-02
申请号：US12130460
申请日：2008-05-30
申请人： Matthew J. Breitwisch , Roger W. Cheek , Jeffrey B. Johnson , Chung H. Lam , Beth A. Rainey , Michael J. Zierak
发明人： Matthew J. Breitwisch , Roger W. Cheek , Jeffrey B. Johnson , Chung H. Lam , Beth A. Rainey , Michael J. Zierak
IPC分类号： H01L21/265
CPC分类号： H01L29/66477 , H01L21/26513 , H01L21/26586 , H01L21/266 , H01L29/1083 , H01L29/6659 , H01L29/66833 , H01L29/7834 , H01L29/792
摘要： The invention provides a method to enhance the programmability of a prompt-shift device, which reduces the programming time to sub-millisecond times, by altering the extension and halo implants, instead of simply omitting the same from one side of the device as is the case in the prior art prompt-shift devices. The invention includes an embodiment in which no additional masks are employed, or one additional mask is employed. The altered extension implant is performed at a reduced ion dose as compared to a conventional extension implant process, while the altered halo implant is performed at a higher ion dose than a conventional halo implant. The altered halo/extension implant shifts the peak of the electrical field to under an extension dielectric spacer.
摘要翻译： 本发明提供了一种通过改变扩展和光晕注入来提高快速移位设备的可编程性的方法，其将编程时间缩短到几毫秒，而不是从设备的一侧简单地省略它 现有技术中的瞬时移位装置。 本发明包括其中不使用附加掩模的实施例，或者采用一个附加掩模。 与常规的延伸植入过程相比，改变的延伸植入物以降低的离子剂量进行，而改变的晕轮植入物以比常规的晕轮植入物更高的离子剂量进行。 改变的光晕/延伸注入将电场的峰值移动到延伸电介质间隔物下方。
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公开(公告)号：US20120120701A1
公开(公告)日：2012-05-17
申请号：US13350823
申请日：2012-01-16
申请人： Brian L. Ji , Chung H. Lam , Robert K. Montoye , Bipin Rajendran
发明人： Brian L. Ji , Chung H. Lam , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C15/00
CPC分类号： G11C15/046 , G11C13/0004
摘要： A content addressable memory device with a plurality of memory cells storing ternary data values of high, low, and don't care. An aspect of the content addressable memory device is the use of first memory elements and second memory elements in the memory cells. The first and second memory elements are electrically coupled in parallel circuit to a match-line. The first memory elements are coupled to first word-lines and the second memory elements are coupled to second word-lines. The first memory elements are configured to store low resistance states if the ternary data value is low and high resistance states if the ternary data value is either high or don't care. The second memory elements are configured to store the low resistance states if the ternary data value is high and the high resistance states if the ternary data value is either low or don't care.
摘要翻译： 一种具有多个存储单元的内容可寻址存储器件，其存储高，低和不关心的三进制数据值。 内容可寻址存储器件的一个方面是在存储器单元中使用第一存储器元件和第二存储器元件。 第一和第二存储器元件以并联电路电耦合到匹配线。 第一存储器元件耦合到第一字线，并且第二存储器元件耦合到第二字线。 如果三进制数据值低，则第一存储器元件被配置为存储低电阻状态，并且如果三进制数据值高或不在乎，则高电阻状态。 如果三进制数据值高，则第二存储器元件被配置为存储低电阻状态，并且如果三进制数据值为低或不关心，则存在高电阻状态。
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64.发明授权Vertical field effect transistor arrays including gate electrodes annularly surrounding semiconductor pillars 有权垂直场效应晶体管阵列，包括围绕半导体柱的环形环形栅电极公开(公告)号：US08110901B2
公开(公告)日：2012-02-07
申请号：US12851232
申请日：2010-08-05
IPC分类号： H01L29/78
CPC分类号： H01L21/823487 , H01L27/088
摘要： Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.
摘要翻译： 垂直场效应晶体管半导体结构和用于制造垂直场效应晶体管半导体结构的方法提供半导体柱阵列。 半导体柱阵列中的每个半导体柱的每个垂直部分具有大于与相邻半导体柱的间隔距离的线宽。 或者，阵列可以包括具有不同线宽的半导体柱，任选地在上述线宽和间隔距离限制的上下文中。 用于制造半导体柱阵列的方法使用最小光刻尺寸的柱掩模层，其在被用作蚀刻掩模之前用至少一个间隔层环形增强。
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65.发明授权Chemical mechanical polishing stop layer for fully amorphous phase change memory pore cell 有权化学机械抛光停止层，用于完全非晶相变记忆孔细胞公开(公告)号：US08012790B2
公开(公告)日：2011-09-06
申请号：US12550062
申请日：2009-08-28
IPC分类号： H01L21/06 , H01L21/108 , H01L21/44 , H01L21/20
CPC分类号： H01L21/31144 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1683 , H01L45/1691
摘要： A method for fabricating a phase change memory pore cell that includes forming a bottom electrode, forming a first dielectric layer on the bottom electrode, forming a sacrificial layer on the first dielectric layer, forming an isolation layer on the sacrificial layer, and forming a second dielectric layer on the isolation layer. The method further includes forming a via overlying the bottom electrode, the via extending to the sacrificial layer, etching through the sacrificial layer to the first dielectric layer to form a pore defined extending through the sacrificial layer and the first dielectric layer, depositing phase change material on the sacrificial layer and into the pore and removing the phase change material formed outside the pore, removing the sacrificial layer to expose the pore, the pore being vertically aligned, and forming a top electrode over the pore.
摘要翻译： 一种相变存储孔单元的制造方法，包括形成底电极，在所述底电极上形成第一电介质层，在所述第一电介质层上形成牺牲层，在所述牺牲层上形成隔离层，形成第二电介质层 隔离层上的介电层。 该方法还包括形成覆盖底部电极的通孔，延伸到牺牲层的通孔，通过牺牲层蚀刻到第一介电层，以形成限定的孔，延伸穿过牺牲层和第一介电层，沉积相变材料 在牺牲层上并进入孔中，除去形成在孔外部的相变材料，去除牺牲层以暴露孔，孔垂直排列，并在孔上形成顶电极。
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公开(公告)号：US20110193045A1
公开(公告)日：2011-08-11
申请号：US12702406
申请日：2010-02-09
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1641 , H01L45/1683
摘要： Techniques for forming a phase change memory cell. An example method includes forming a bottom electrode within a substrate. The method includes forming a phase change layer above the bottom electrode. The method includes forming a capping layer and an insulator layer. The method includes crystallizing the phase change material in the phase change layer so that the phase change layer is void free. The method further comprises heating the phase change material in the phase change layer from the bottom electrode and as a result the phase change layer is crystallized from the bottom to the top. In one embodiment, a rapid thermal anneal (RTA) is applied for crystallizing the phase change material.
摘要翻译： 形成相变存储单元的技术。 一种示例性方法包括在衬底内形成底部电极。 该方法包括在底部电极上形成相变层。 该方法包括形成覆盖层和绝缘体层。 该方法包括使相变层中的相变材料结晶，使得相变层无空隙。 该方法还包括从底部电极加热相变层中的相变材料，结果相变层从底部到顶部结晶。 在一个实施例中，应用快速热退火（RTA）以使相变材料结晶。
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公开(公告)号：US07981755B2
公开(公告)日：2011-07-19
申请号：US11924073
申请日：2007-10-25
IPC分类号： H01L21/331 , H01L21/44
CPC分类号： H01L21/76843 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/148 , H01L45/16 , H01L45/1675 , H01L45/1683
摘要： The present invention in one embodiment provides a method of manufacturing an electrode that includes providing at least one metal stud positioned in a via extending into a first dielectric layer, wherein an electrically conductive liner is positioned between at least a sidewall of the via and the at least one metal stud; recessing an upper surface of the at least one metal stud below an upper surface of the first dielectric layer to provide at least one recessed metal stud; and forming a second dielectric atop the at least one recessed metal stud, wherein an upper surface of the electrically conductive liner is exposed.
摘要翻译： 本发明在一个实施例中提供了一种制造电极的方法，其包括提供定位在延伸到第一介电层中的通孔中的至少一个金属柱，其中导电衬垫定位在通孔的至少侧壁和在 最少一个金属螺柱; 将所述至少一个金属螺柱的上表面凹陷在所述第一介电层的上表面下方，以提供至少一个凹入的金属柱; 以及在所述至少一个凹入的金属螺柱的顶部上形成第二电介质，其中所述导电衬垫的上表面被暴露。
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公开(公告)号：US07965537B2
公开(公告)日：2011-06-21
申请号：US12491816
申请日：2009-06-25
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2013/0083 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/16 , Y10T29/49002
摘要： A phase change memory device and a method for programming the same. The method includes determining a maximum possible resistance for the memory cells in the phase change memory device. The method includes determining a high resistance state for the memory cells in the phase change memory device. The method includes receiving a request to program a target memory cell in the phase change memory device to the high resistance state. The method also includes resetting the target memory cell in the phase change memory device to the high resistance state such that the high resistance state of the target memory cell is of less resistance than the maximum possible resistance. In one embodiment of the invention, the high resistance state for the memory cells in the phase change memory device is at least 10% less than the maximum possible resistance.
摘要翻译： 相变存储器件及其编程方法。 该方法包括确定相变存储器件中的存储器单元的最大可能电阻。 该方法包括确定相变存储器件中存储单元的高电阻状态。 该方法包括接收将相变存储器件中的目标存储单元编程为高电阻状态的请求。 该方法还包括将相变存储器件中的目标存储单元重置为高电阻状态，使得目标存储单元的高电阻状态的阻抗比最大可能的电阻小。 在本发明的一个实施例中，相变存储器件中的存储单元的高电阻状态比最大可能电阻小至少10％。
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公开(公告)号：US20110116307A1
公开(公告)日：2011-05-19
申请号：US12619362
申请日：2009-11-16
申请人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran , Simone Raoux , Alejandro G. Schrott , Daniel Krebs
发明人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran , Simone Raoux , Alejandro G. Schrott , Daniel Krebs
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/0069 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： A phase change memory cell that includes a bottom electrode, a top electrode separated from the bottom electrode, and growth-dominated phase change material deposited between the bottom electrode and the top electrode and contacting the bottom electrode and the top electrode and surrounded by insulation material at sidewalls thereof. The phase change memory cell in a reset state only includes an amorphous phase of the growth-dominated phase change material within an active volume of the phase change memory cell.
摘要翻译： 一种相变存储单元，包括底部电极，从底部电极分离的顶部电极和沉积在底部电极和顶部电极之间的生长主导的相变材料，并且与底部电极和顶部电极接触并被绝缘材料包围 在其侧壁。 处于复位状态的相变存储单元仅包括在相变存储单元的有效体积内的以生长为主的相变材料的非晶相。
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公开(公告)号：US07888164B2
公开(公告)日：2011-02-15
申请号：US12538120
申请日：2009-08-08
IPC分类号： H01L21/02
CPC分类号： H01L45/122 , H01L45/06 , H01L45/1206 , H01L45/1286 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A method of fabricating a programmable via structure is provided. The method includes providing a patterned heating material on a surface of an oxide layer. The oxide layer is located above a semiconductor substrate. A patterned dielectric material is formed having a least one via on a surface of the patterned heating material. The at least one via is filled with a phase change material such that a lower surface of the phase change material is in direct contact with a portion of the patterned heating material. A patterned diffusion barrier is formed on an exposed surface of the at least one via filled with the phase change material. A method of programmable a programmable via structure made by the method is also disclosed.
摘要翻译： 提供一种制造可编程通孔结构的方法。 该方法包括在氧化物层的表面上提供图案化的加热材料。 氧化物层位于半导体衬底之上。 在图案化加热材料的表面上形成具有至少一个通孔的图案化电介质材料。 至少一个通孔填充有相变材料，使得相变材料的下表面与图案化加热材料的一部分直接接触。 图案化的扩散阻挡层形成在填充有相变材料的至少一个通孔的暴露表面上。 还公开了一种通过该方法制成的可编程通孔结构的方法。
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