公开(公告)号：US10047439B2

公开(公告)日：2018-08-14

申请号：US13314850

申请日：2011-12-08

申请人： Po-Feng Tsai ,  Chia-Tong Ho ,  Sunny Wu ,  Jo Fei Wang ,  Jong-I Mou ,  Chin-Hsiang Lin

发明人： Po-Feng Tsai ,  Chia-Tong Ho ,  Sunny Wu ,  Jo Fei Wang ,  Jong-I Mou ,  Chin-Hsiang Lin

IPC分类号： G06F19/00 ,  C23C16/52 ,  H01L21/66

摘要： A method and system for removing control action effects from inline measurement data for tool condition monitoring is disclosed. An exemplary method includes determining a control action effect that contributes to an inline measurement, wherein the inline measurement indicates a wafer characteristic of a wafer processed by a process tool; and evaluating the inline measurement without the control action effect contribution to determine a condition of the process tool.

公开(公告)号：US09786471B2

公开(公告)日：2017-10-10

申请号：US13337418

申请日：2011-12-27

申请人： Ying Xiao ,  Chin-Hsiang Lin

发明人： Ying Xiao ,  Chin-Hsiang Lin

IPC分类号： H01J37/32 ,  G03F7/42 ,  H01L21/311

CPC分类号： H01J37/321 ,  G03F7/427 ,  H01J37/32596 ,  H01J37/32706 ,  H01J37/32807 ,  H01J37/32889 ,  H01J37/32899 ,  H01L21/31138

摘要： In some embodiments, the present disclosure relates to a plasma etching system having direct and localized plasma sources in communication with a processing chamber. The direct plasma is operated to provide a direct plasma to the processing chamber for etching a semiconductor workpiece. The direct plasma has a high potential, formed by applying a large bias voltage to the workpiece. After etching is completed the bias voltage and direct plasma source are turned off. The localized plasma source is then operated to provide a low potential, localized plasma to a position within the processing chamber that is spatially separated from the workpiece. The spatial separation results in formation of a diffused plasma having a zero/low potential that is in contact with the workpiece. The zero/low potential of the diffused plasma allows for reactive ashing to be performed, while mitigating workpiece damage resulting from ion bombardment caused by positive plasma potentials.

公开(公告)号：US09349660B2

公开(公告)日：2016-05-24

申请号：US13308644

申请日：2011-12-01

申请人： Po-Feng Tsai ,  Chia-Tong Ho ,  Sunny Wu ,  Jo Fei Wang ,  Jong-I Mou ,  Chin-Hsiang Lin

发明人： Po-Feng Tsai ,  Chia-Tong Ho ,  Sunny Wu ,  Jo Fei Wang ,  Jong-I Mou ,  Chin-Hsiang Lin

IPC分类号： G06F19/00 ,  H01L21/66

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for monitoring a process tool of an integrated circuit manufacturing system are disclosed. An exemplary method includes defining zones of an integrated circuit manufacturing process tool; grouping parameters of the integrated circuit manufacturing process tool based on the defined zones; and evaluating a condition of the integrated circuit manufacturing process tool based on the grouped parameters.

摘要翻译： 公开了一种用于监控集成电路制造系统的处理工具的系统和方法。 示例性方法包括限定集成电路制造工艺工具的区域; 基于定义的区域对集成电路制造工艺工具进行分组参数; 并基于分组的参数来评估集成电路制造处理工具的状况。

公开(公告)号：US09250619B2

公开(公告)日：2016-02-02

申请号：US13311601

申请日：2011-12-06

申请人： Chih-Wei Hsu ,  Mei-Jen Wu ,  Yen-Di Tsen ,  Jo Fei Wang ,  Jong-I Mou ,  Chin-Hsiang Lin

发明人： Chih-Wei Hsu ,  Mei-Jen Wu ,  Yen-Di Tsen ,  Jo Fei Wang ,  Jong-I Mou ,  Chin-Hsiang Lin

IPC分类号： G06F19/00 ,  G05B19/18 ,  H01L21/66

CPC分类号： G05B19/18 ,  G05B2219/45031 ,  H01L22/20

摘要： A system and method of automatically calculating boundaries for a semiconductor fabrication process. The method includes selecting a first parameter for monitoring during a semiconductor fabrication process. A first set of values for the first parameter are received and a group value of the first set is determined. Each value in the first set of values is normalized. A first weighting factor is selected based on a number of values in the first set. The embodiment also includes generating a first and a second boundary value as a function of the weighting factor, the first set normalized values and the group value of the first set and applying the first and second boundary values to control the semiconductor fabrication process.

摘要翻译： 一种自动计算半导体制造工艺边界的系统和方法。 该方法包括在半导体制造过程中选择用于监测的第一参数。 接收第一参数的第一组值，并确定第一组的组值。 第一组值中的每个值都被归一化。 基于第一组中的值的数量来选择第一加权因子。 该实施例还包括根据加权因子，第一集合归一化值和第一组的组值产生第一和第二边界值，并施加第一和第二边界值以控制半导体制造过程。

公开(公告)号：US09111982B2

公开(公告)日：2015-08-18

申请号：US13539243

申请日：2012-06-29

申请人： I-Hsiung Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee ,  Chin-Hsiang Lin

发明人： I-Hsiung Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee ,  Chin-Hsiang Lin

IPC分类号： H01L21/683

CPC分类号： H01L21/0201 ,  H01L21/6835 ,  H01L2221/6834 ,  H01L2221/68381

摘要： A wafer assembly includes a process wafer and a carrier wafer. Integrated circuits are formed on the process wafer. The carrier wafer is bonded to the process wafer. The carrier wafer has at least one alignment mark.

摘要翻译： 晶片组件包括处理晶片和载体晶片。 集成电路形成在处理晶片上。 载体晶片结合到工艺晶片。 载体晶片具有至少一个对准标记。

公开(公告)号：US09026241B2

公开(公告)日：2015-05-05

申请号：US13404676

申请日：2012-02-24

申请人： Wen-Cheng Yang ,  Chung-En Kao ,  You-Hua Chou ,  Ming-Chih Tsai ,  Chen-Chia Chiang ,  Bo-Hung Lin ,  Chin-Hsiang Lin

发明人： Wen-Cheng Yang ,  Chung-En Kao ,  You-Hua Chou ,  Ming-Chih Tsai ,  Chen-Chia Chiang ,  Bo-Hung Lin ,  Chin-Hsiang Lin

IPC分类号： G06F19/00 ,  G05B9/03

CPC分类号： G05B9/03 ,  G05B23/0237 ,  G05B2219/37533 ,  G05B2219/45031

摘要： The present disclosure relates to semiconductor tool monitoring system having multiple sensors configured to concurrently and independently monitor processing conditions of a semiconductor manufacturing tool. In some embodiments, the disclosed tool monitoring system comprises a first sensor system configured to monitor one or more processing conditions of a semiconductor manufacturing tool and to generate a first monitoring response based thereupon. A redundant, second sensor system is configured to concurrently monitor the one or more processing conditions of the manufacturing tool and to generate a second monitoring response based thereupon. A comparison element is configured to compare the first and second monitoring responses, and if the responses deviate from one another (e.g., have a deviation greater than a threshold value) to generate a warning signal. By comparing the first and second monitoring responses, errors in the sensor systems can be detected in real time, thereby preventing yield loss.

摘要翻译： 本公开涉及具有多个传感器的半导体工具监视系统，其被配置为同时且独立地监视半导体制造工具的处理条件。 在一些实施例中，所公开的工具监控系统包括被配置为监视半导体制造工具的一个或多个处理条件并基于此产生第一监视响应的第一传感器系统。 冗余的第二传感器系统被配置为同时监视制造工具的一个或多个处理条件并且基于此产生第二监视响应。 比较元件被配置为比较第一和第二监测响应，以及如果响应彼此偏离（例如，具有大于阈值的偏差）以产生警告信号。 通过比较第一和第二监测响应，可以实时检测传感器系统中的误差，从而防止产量损失。

公开(公告)号：US08906599B2

公开(公告)日：2014-12-09

申请号：US13473695

申请日：2012-05-17

申请人： Yu-Mei Liu ,  Chin-Hsiang Lin ,  Heng-Hsin Liu ,  Heng-Jen Lee ,  I-Hsiung Huang ,  Chih-Wei Lin

发明人： Yu-Mei Liu ,  Chin-Hsiang Lin ,  Heng-Hsin Liu ,  Heng-Jen Lee ,  I-Hsiung Huang ,  Chih-Wei Lin

IPC分类号： G03F7/20

CPC分类号： G03F7/70358

摘要： A method and system to improve scanner throughput is provided. An image from a reticle is projected onto a substrate using a continuous linear scanning procedure in which an entire column of die or cells of die is scanned continuously, i.e. without stepping to a different location. Each scan includes translating a substrate with respect to a fixed beam. While the substrate is translated, the reticle is also translated. When a first die or cell of die is projected onto the substrate, the reticle translates along a direction opposite the scan direction and as the scan continues along the same direction, the reticle then translates in the opposite direction of the substrate thereby forming an inverted pattern on the next die or cell. The time associated with exposing the substrate is minimized as the stepping operation only occurs after a complete column of cells is scanned.

摘要翻译： 提供了一种提高扫描仪吞吐量的方法和系统。 使用连续线性扫描程序将来自掩模版的图像投影到基板上，其中连续扫描整列管芯或裸片的单元，即不进入不同的位置。 每个扫描包括相对于固定光束平移衬底。 当底物被翻译时，掩模版也被翻译。 当模具的第一裸片或裸片投影到衬底上时，标线沿着与扫描方向相反的方向平移，并且随着扫描沿着相同的方向继续，标线片然后沿着衬底的相反方向平移，从而形成倒置图案 在下一个死亡或细胞。 与曝光底物相关的时间最小化，因为步进操作仅在扫描完整的单元格列之后才发生。

公开(公告)号：US08704224B2

公开(公告)日：2014-04-22

申请号：US13241634

申请日：2011-09-23

申请人： An-Chun Tu ,  Chen-Ming Huang ,  Chih-Jen Wu ,  Chin-Hsiang Lin

发明人： An-Chun Tu ,  Chen-Ming Huang ,  Chih-Jen Wu ,  Chin-Hsiang Lin

IPC分类号： H01L23/10

CPC分类号： G01R31/2644 ,  G01R31/2884 ,  H01L22/14 ,  H01L22/32 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A resistive test structure that includes a semiconductor substrate with an active region, a gate stack formed over the active region, a first electrical contact in communication with the active region on opposing sides of the gate stack, the first electrical contact providing an electrical short across a first dimension of the gate stack, and a second electrical contact in communication with the active region on the opposing sides of the gate stack, the second electrical contact providing an electrical short across the first dimension of the gate stack, the first and second electrical contacts spaced along a second dimension of the gate stack perpendicular to the first dimension.

摘要翻译： 一种电阻测试结构，其包括具有有源区的半导体衬底，形成在有源区上的栅极叠层，与栅极堆叠的相对侧上的有源区连通的第一电触点，第一电触点提供跨越 栅极堆叠的第一尺寸和与栅极堆叠的相对侧上的有源区域连通的第二电触点，第二电触点跨过栅极堆叠的第一维度提供电短路，第一和第二电极 接触件沿垂直于第一尺寸的栅极堆叠的第二尺寸间隔开。

公开(公告)号：US20140017604A1

公开(公告)日：2014-01-16

申请号：US13550036

申请日：2012-07-16

申请人： Yung-Yao Lee ,  Ying Ying Wang ,  Heng-Hsin Liu ,  Chin-Hsiang Lin

发明人： Yung-Yao Lee ,  Ying Ying Wang ,  Heng-Hsin Liu ,  Chin-Hsiang Lin

IPC分类号： G03F7/20

CPC分类号： G03F7/70633

摘要： A process for use in lithography, such as photolithography for patterning a semiconductor wafer, is disclosed. The process includes receiving an incoming semiconductor wafer having various features and layers formed thereon. A unit-induced overlay (uniiOVL) correction is received and a deformation measurement is performed on the incoming semiconductor wafer in an overlay module. A deformation-induced overlay (defiOVL) correction is generated from the deformation measurement results by employing a predetermined algorithm on the deformation measurement results. The defiOVL and uniiOVL corrections are fed-forward to an exposure module and an exposure process is performed on the incoming semiconductor wafer.

摘要翻译： 公开了一种用于光刻的方法，例如用于图案化半导体晶片的光刻技术。 该方法包括接收具有形成在其上的各种特征和层的输入半导体晶片。 接收单元引起的覆盖（uniOVL）校正，并且在覆盖模块中对输入的半导体晶片进行变形测量。 通过对变形测量结果采用预定的算法，从变形测量结果生成变形诱导的覆盖（defiOVL）校正。 defiVV和unioVL校正被反馈到曝光模块，并且对输入的半导体晶片进行曝光处理。

公开(公告)号：US20130306621A1

公开(公告)日：2013-11-21

申请号：US13471583

申请日：2012-05-15

申请人： Chih-Tien Chang ,  Sunny Wu ,  Jo Fei Wang ,  Jong-I Mou ,  Chin-Hsiang Lin

发明人： Chih-Tien Chang ,  Sunny Wu ,  Jo Fei Wang ,  Jong-I Mou ,  Chin-Hsiang Lin

IPC分类号： H05B1/02

CPC分类号： H01L22/26 ,  H01L21/324 ,  H01L21/67115 ,  H01L21/67248 ,  H05B1/0233

摘要： An apparatus, a system and a method are disclosed. An exemplary apparatus includes a wafer processing chamber. The apparatus further includes radiant heating elements disposed in different zones and operable to heat different portions of a wafer located within the wafer processing chamber. The apparatus further includes sensors disposed outside the wafer processing chamber and operable to monitor energy from the radiant heating elements disposed in the different zones. The apparatus further includes a computer configured to utilize the sensors to characterize the radiant heating elements disposed in the different zones and to provide a calibration for the radiant heating elements disposed in the different zones such that a substantially uniform temperature profile is maintained across a surface of the wafer.

摘要翻译： 公开了一种装置，系统和方法。 示例性装置包括晶片处理室。 该设备还包括设置在不同区域中的辐射加热元件，其可操作以加热位于晶片处理室内的晶片的不同部分。 该装置还包括设置在晶片处理室外部的传感器，其可操作以监测来自设置在不同区域中的辐射加热元件的能量。 该装置还包括计算机，其被配置为利用传感器来表征设置在不同区域中的辐射加热元件，并且为放置在不同区域中的辐射加热元件提供校准，使得基本上均匀的温度分布保持在 晶圆。