公开(公告)号：US12125675B2

公开(公告)日：2024-10-22

申请号：US17475721

申请日：2021-09-15

Applicant: Applied Materials, Inc.

Inventor： Ruitong Xiong ,  Bo Xie ,  Xiaobo Li ,  Yijun Liu ,  Li-Qun Xia

IPC: H01L21/02 ,  C23C16/40 ,  C23C16/505 ,  C23C16/56 ,  H01J37/32

CPC classification number: H01J37/32146 ,  C23C16/401 ,  C23C16/505 ,  C23C16/56 ,  H01J37/32522 ,  H01J37/32889 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02348 ,  H01J2237/332

Abstract: Exemplary semiconductor processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include forming a plasma of the silicon-containing precursor in the processing region. The plasma may be at least partially formed by an RF power operating at between about 50 W and 1,000 W, at a pulsing frequency below about 100,000 Hz, and at a duty cycle between about 5% and 95%. The methods may include forming a layer of material on the substrate. The layer of material may include a silicon-containing material.

公开(公告)号：US20180166307A1

公开(公告)日：2018-06-14

申请号：US15832380

申请日：2017-12-05

Applicant: Lam Research Corporation

Inventor： Matthew Davis

IPC: H01L21/67 ,  H01L21/66 ,  H01J37/32 ,  C23C16/52 ,  C23C16/44

CPC classification number: H01L21/67288 ,  C23C16/4401 ,  C23C16/52 ,  H01J37/32853 ,  H01J37/32889 ,  H01J37/32935 ,  H01J37/3299 ,  H01L22/12 ,  H01L22/24

Abstract: Apparatuses and methods for improved substrate defect detection is provided. Substrate defects may be detected, possibly with defect detection equipment such as laser metrology equipment. Defects smaller than the detection limit of the detection equipment may be decorated with a layer of material to increase the effective sizes of the defects. The thickness and composition of the material deposited may be tuned depending on the composition of the substrate and the defects. The composition of the detected defects may be identified with defect identification equipment. The defect identification equipment may be an electron generating apparatus and the composition of the defects may be identified from the interaction of the electrons with the defect. The deposited material may be removed either before or during the defect identification phase to aid in the identification of the defect composition.

公开(公告)号：US09922854B2

公开(公告)日：2018-03-20

申请号：US13098253

申请日：2011-04-29

Applicant: Shinichi Kurita ,  Jozef Kudela ,  Suhail Anwar ,  John M. White ,  Dong-Kil Yim ,  Hans Georg Wolf ,  Dennis Zvalo ,  Makoto Inagawa ,  Ikuo Mori

Inventor： Shinichi Kurita ,  Jozef Kudela ,  Suhail Anwar ,  John M. White ,  Dong-Kil Yim ,  Hans Georg Wolf ,  Dennis Zvalo ,  Makoto Inagawa ,  Ikuo Mori

IPC: C23C16/458 ,  C23C16/46 ,  C23C16/511 ,  C23C16/54 ,  H01J37/32 ,  H01L21/67 ,  H01L21/677

CPC classification number: H01L21/67712 ,  C23C16/4587 ,  C23C16/46 ,  C23C16/463 ,  C23C16/511 ,  C23C16/54 ,  H01J37/32192 ,  H01J37/3222 ,  H01J37/32513 ,  H01J37/32522 ,  H01J37/32889 ,  H01J37/32899 ,  H01L21/67098 ,  H01L21/67126 ,  H01L21/67173 ,  H01L21/6719 ,  H01L21/67201

Abstract: The present invention generally relates to a vertical CVD system having a processing chamber that is capable of processing multiple substrates. The multiple substrates are disposed on opposite sides of the processing source within the processing chamber, yet the processing environments are not isolated from each other. The processing source is a horizontally centered vertical plasma generator that permits multiple substrates to be processed simultaneously on either side of the plasma generator, yet independent of each other. The system is arranged as a twin system whereby two identical processing lines, each with their own processing chamber, are arranged adjacent to each other. Multiple robots are used to load and unload the substrates from the processing system. Each robot can access both processing lines within the system.

公开(公告)号：US09748101B2

公开(公告)日：2017-08-29

申请号：US14430988

申请日：2013-09-27

Applicant: Tokyo Electron Limited

Inventor： Makoto Muramatsu ,  Takahiro Kitano ,  Tadatoshi Tomita ,  Keiji Tanouchi ,  Soichiro Okada

IPC: G03B27/32 ,  H01L21/027 ,  G03F7/16 ,  G03F7/40 ,  G03F7/00 ,  H01J37/32 ,  H01L21/311 ,  H01L21/67

CPC classification number: H01L21/0274 ,  G03F7/0002 ,  G03F7/16 ,  G03F7/405 ,  H01J37/32889 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/6715 ,  H01L21/67253

Abstract: The present invention is configured to: form, on a substrate, a neutral layer having an intermediate affinity to a hydrophilic polymer and a hydrophobic polymer; form a resist pattern by performing exposure processing on a resist film formed on the neutral layer and then developing the resist film after the exposure processing; perform a surface treatment on the resist pattern by supplying an organic solvent having a polarity to the resist pattern; apply the block copolymer onto the neutral layer; and phase-separate the block copolymer on the neutral layer into the hydrophilic polymer and the hydrophobic polymer.

公开(公告)号：US09721839B2

公开(公告)日：2017-08-01

申请号：US14738389

申请日：2015-06-12

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Mohammad Kamruzzaman Chowdhury ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/02 ,  H01L21/82 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/67 ,  H01J37/32

CPC classification number: H01L21/82 ,  H01J37/32889 ,  H01J37/32899 ,  H01J2237/334 ,  H01J2237/335 ,  H01L21/02057 ,  H01L21/02076 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31127 ,  H01L21/32131 ,  H01L21/67207 ,  H01L21/78

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer including a plurality of integrated circuits includes forming a water soluble mask above the semiconductor wafer, the water soluble mask covering and protecting the integrated circuits. The method also includes baking the water soluble mask to increase the etch resistance of the water soluble mask. The method also includes, subsequent to baking the water soluble mask, patterning the water soluble mask with a laser scribing process to provide a water soluble patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The method also includes plasma etching the semiconductor wafer through the gaps in the water soluble patterned mask to singulate the integrated circuits.

公开(公告)号：US09698106B2

公开(公告)日：2017-07-04

申请号：US15073551

申请日：2016-03-17

Applicant: Infineon Technologies Austria AG

Inventor： Kae-Horng Wang ,  Francisco Javier Santos Rodriguez ,  Michael Knabl ,  Guenther Koffler

IPC: H01L21/67 ,  H01L23/00 ,  H01L21/02 ,  C23C16/34 ,  C23C16/40 ,  C23C16/50 ,  C23C18/16 ,  G03F7/16 ,  G03F7/20 ,  G03F7/26 ,  H01J37/32 ,  H01L21/311 ,  H01L21/288 ,  H01L23/485 ,  H01L27/146

CPC classification number: H01L21/02274 ,  C23C16/34 ,  C23C16/40 ,  C23C16/50 ,  C23C18/1619 ,  G03F7/16 ,  G03F7/20 ,  G03F7/26 ,  H01J37/32889 ,  H01J2237/3321 ,  H01L21/02035 ,  H01L21/02038 ,  H01L21/288 ,  H01L21/31144 ,  H01L21/6715 ,  H01L21/67225 ,  H01L21/6723 ,  H01L23/485 ,  H01L23/564 ,  H01L27/14683 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various techniques, methods, devices and apparatus are provided where an isolation layer is provided at a peripheral region of the substrate, and one or more metal layers are deposited onto the substrate.

公开(公告)号：US20170186634A1

公开(公告)日：2017-06-29

申请号：US15071606

申请日：2016-03-16

Applicant: HITACHI KOKUSAI ELECTRIC INC.

Inventor： Yoshihiko YANAGISAWA ,  Masaaki UENO ,  Naofumi OHASHI

IPC: H01L21/67 ,  H01L21/02 ,  C23C16/46 ,  H01L21/687 ,  H01J37/32 ,  C23C16/455

CPC classification number: H01L21/67196 ,  C23C16/4412 ,  C23C16/455 ,  C23C16/45523 ,  C23C16/45561 ,  C23C16/45565 ,  C23C16/4585 ,  C23C16/4586 ,  C23C16/46 ,  H01J37/32009 ,  H01J37/3244 ,  H01J37/32467 ,  H01J37/32522 ,  H01J37/32724 ,  H01J37/32807 ,  H01J37/32889 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/67103 ,  H01L21/6719 ,  H01L21/67742 ,  H01L21/68785 ,  H01L21/68792

Abstract: A substrate processing apparatus, including: a process chamber configured to process a substrate, a transfer chamber adjoining the process chamber, a shaft installed in the transfer chamber, a substrate mounting stand connected to the shaft and including a heating part, a first thermal insulation part installed in a wall of the transfer chamber at a side of the process chamber, and a second thermal insulation part installed in the shaft at a side of the substrate mounting stand.

公开(公告)号：US20170178920A1

公开(公告)日：2017-06-22

申请号：US15449799

申请日：2017-03-03

Applicant: Lam Research Corporation

Inventor： Nikhil Dole ,  Eric A. Hudson ,  George Matamis

IPC: H01L21/3065 ,  C23C16/52 ,  C23C16/455 ,  H01L21/67 ,  H01J37/32

CPC classification number: H01L21/30655 ,  H01J37/32091 ,  H01J37/32137 ,  H01J37/32889 ,  H01J37/32899 ,  H01J2237/3321 ,  H01J2237/334 ,  H01J2237/3347 ,  H01L21/02112 ,  H01L21/02118 ,  H01L21/0212 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31116 ,  H01L21/67069 ,  H01L28/00

Abstract: Methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate are provided. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective film on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective film may be deposited under different conditions (e.g., pressure, duration of reactant delivery, duration of plasma exposure, RF power, and/or RF duty cycle, etc.) in different deposition operations. Such conditions may affect the degree of conformality at which the protective film forms. In various embodiments, one or more protective films may be sub-conformal. In these or other embodiments, one or more other protective films may be conformal.

公开(公告)号：US09676010B2

公开(公告)日：2017-06-13

申请号：US14904743

申请日：2014-07-15

Applicant: Universidade Federal De Santa Catarina (UFSC) ,  Whirlpool S.A.

Inventor： Roberto Binder ,  Aloisio Nelmo Klein ,  Cristiano Binder ,  Gisele Hammes

IPC: C23F1/00 ,  B08B7/00 ,  H01J37/32 ,  H01L21/67 ,  B22F3/00 ,  B22F3/24

CPC classification number: B08B7/0035 ,  B22F3/003 ,  B22F3/24 ,  B22F2003/241 ,  B22F2003/248 ,  H01J37/32009 ,  H01J37/3244 ,  H01J37/32522 ,  H01J37/32834 ,  H01J37/32889 ,  H01J37/32899 ,  H01J2237/335 ,  H01L21/67109 ,  H01L21/67173 ,  H01L21/6719

Abstract: The plasma reactor comprises a reaction chamber (23) connectable to a source of ionizable gases (25) and to a heating device (80), said reactor (10) being subjected to the phases of heating (A), cleaning (L) and/or surface treatment (S), cooling (R), unloading (D) and loading (C) of metallic pieces (1). The installation comprises: at least two reactors (10), each being selectively and alternately connected to: the same source of ionizable gases (25); the same vacuum source (60); the same electrical energy source (50); and to the same heating device (80), the latter being displaceable between operative positions, in each of which surrounding laterally and superiorly a respective reactor (10), while the latter is in its heating phase (A) and cleaning phase (L) and/or in the surface treatment phase (S) of the metallic pieces (1).

公开(公告)号：US09566802B2

公开(公告)日：2017-02-14

申请号：US14656552

申请日：2015-03-12

Applicant: Ricoh Company, Ltd.

Inventor： Kengo Tsubaki ,  Satoshi Katoh

IPC: B41J2/17 ,  B41J11/00 ,  H05H1/24 ,  B41M1/36 ,  H01J37/32 ,  B41J3/60

CPC classification number: B41J11/0015 ,  B41J3/60 ,  B41M1/36 ,  H01J37/32532 ,  H01J37/32889 ,  H01J2237/338 ,  H05H1/2406 ,  H05H2001/2412

Abstract: A treated object modifying apparatus includes a plasma-treating unit that includes a first electrode unit, a second electrode unit, and a dielectric that is interposed between the first electrode unit and the second electrode unit, and that plasma-treats a treated object positioned between the first electrode unit and the dielectric; and a controlling unit that controls the plasma-treating unit so that the amount of plasma energy delivered to any one of sides of the treated object in a duplex treatment that are performed with the one side of the treated object facing the first electrode unit and with the other side of the treated object facing the first electrode unit is different from the amount of plasma energy delivered to any one of the sides of the treated object in a simplex treatment that is performed with the one side of the treated object facing the first electrode unit.

Abstract translation: 处理对象修改装置包括等离子体处理单元，其包括插入在第一电极单元和第二电极单元之间的第一电极单元，第二电极单元和电介质，并且等离子体处理位于 第一电极单元和电介质; 以及控制单元，其控制等离子体处理单元，使得在处理对象的一侧面对第一电极单元执行的双相处理中输送到处理对象的任何一侧的等离子体能量的量，并且与 面对第一电极单元的被处理物体的另一侧不同于在处理物体的面对第一电极的一侧进行的单面处理中输送到被处理物体的任一侧的等离子体能量的量 单元。