公开(公告)号：US07779215B2

公开(公告)日：2010-08-17

申请号：US10906748

申请日：2005-03-04

申请人： Ming-Shi Liou ,  Bowei Hsieh ,  Jiin Lai

发明人： Ming-Shi Liou ,  Bowei Hsieh ,  Jiin Lai

IPC分类号： G06F12/06

CPC分类号： G06F13/1684 ,  G11C2207/2281

摘要： A method for utilizing the multi-channel transmission bandwidth in an asymmetrically arranged memory is provides. The present invention defines symmetrically arranged parts of the memory ranks of the memory as a virtual ranks. If data is stored in symmetrically arranged memory ranks of the memory, channels corresponding to the symmetrically arranged memory ranks could be simultaneously utilized to transfer data. If data is stored in an asymmetrically arranged memory rank of the memory, the channel corresponding to the asymmetrically arranged memory rank could only be utilized to transfer data.

摘要翻译： 提供了一种在不对称布置的存储器中利用多通道传输带宽的方法。 本发明将存储器的存储器级别的对称布置部分定义为虚拟等级。 如果数据存储在存储器的对称布置的存储器级中，则对应于对称排列的存储器级别的通道可以同时用于传送数据。 如果数据被存储在存储器的不对称排列的存储器级中，则对应于不对称布置的存储器级的通道只能用于传送数据。

公开(公告)号：US07624286B2

公开(公告)日：2009-11-24

申请号：US11215222

申请日：2005-08-30

申请人： Ruei-Ling Lin ,  Jiin Lai ,  Hung-Yi Kuo

发明人： Ruei-Ling Lin ,  Jiin Lai ,  Hung-Yi Kuo

IPC分类号： G06F1/00 ,  G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/172

摘要： A power state management method of north bridge. The north bridge monitors power transition state of processor; then adjusting operating clocks and operating voltage of the processor and the main memory according to the determined power state to saving power consumption.

摘要翻译： 北桥电力状态管理方法。 北桥监控处理器的电源转换状态; 然后根据确定的功率状态调整处理器和主存储器的工作时钟和工作电压，以节省功耗。

公开(公告)号：US20080104320A1

公开(公告)日：2008-05-01

申请号：US11854576

申请日：2007-09-13

申请人： Chun-Yuan Su ,  Chau-Chad Tsai ,  Jiin Lai

发明人： Chun-Yuan Su ,  Chau-Chad Tsai ,  Jiin Lai

IPC分类号： G06F12/02

CPC分类号： G06F13/4027 ,  G06F11/1076 ,  G06F2211/1054

摘要： A Northbridge providing RAID access is coupled among a central processing unit, a system memory, and a Southbridge. Furthermore, the Northbridge further couples to a RAID through a Southbridge. The Northbridge include a RAID accelerator for performing RAID operations according to RAID control commands which are stored in a register.

摘要翻译： 在中央处理单元，系统存储器和南桥之间耦合提供RAID访问的北桥。 此外，北桥通过南桥进一步融合到RAID。 北桥包含RAID加速器，用于根据存储在寄存器中的RAID控制命令进行RAID操作。

公开(公告)号：US20070101026A1

公开(公告)日：2007-05-03

申请号：US11538747

申请日：2006-10-04

申请人： Jiin Lai ,  Chun-Yuan Su ,  Yuan-Zong Cheng

发明人： Jiin Lai ,  Chun-Yuan Su ,  Yuan-Zong Cheng

IPC分类号： G06F3/00 ,  G06F5/00

CPC分类号： G06F13/4059 ,  G06F2213/0024

摘要： In a data buffer space configuration method for requesting data from a target device via a bus, a device count of master device coupled to the bus is detected by the operating system. Then, a first data buffer space is configured to the master device if the device count is not greater than a threshold. On the other hand, a second data buffer space is configured to the master device if the device count is greater than the threshold.

摘要翻译： 在用于经由总线从目标设备请求数据的数据缓冲器空间配置方法中，操作系统检测耦合到总线的主设备的设备数量。 然后，如果设备计数不大于阈值，则将第一数据缓冲区配置给主设备。 另一方面，如果设备计数大于阈值，则将第二数据缓冲空间配置到主设备。

公开(公告)号：US07136955B2

公开(公告)日：2006-11-14

申请号：US10980624

申请日：2004-11-03

申请人： Chun-Yuan Su ,  Jiin Lai ,  Chau-Chad Tsai ,  Chi-Che Tsai

发明人： Chun-Yuan Su ,  Jiin Lai ,  Chau-Chad Tsai ,  Chi-Che Tsai

IPC分类号： G06F13/00 ,  G06F13/20 ,  G06F13/36

CPC分类号： G06F13/385 ,  G06F2213/0024

摘要： An expansion adapter is used to communicate both PCI and AGP devices to the north bridge chip of a computer. The expansion adapter includes a first AGP bus control module communicable with the north bridge chip via a first AGP bus, and a second AGP bus control module in communication with the first AGP bus control module, communicable with an AGP device via a second AGP bus. The identifying codes of the first and second AGP bus control modules are set to show no AGP device function in order to allow the AGP device to communicate with the north bridge chip via the expansion adapter. The expansion adapter further includes a PCI bus control module in communication with the PCI device and the first AGP bus control module for controlling data transmission between the first AGP bus control module and the PCI device.

摘要翻译： 扩展适配器用于将PCI和AGP设备通信到计算机的北桥芯片。 扩展适配器包括经由第一AGP总线与北桥芯片通信的第一AGP总线控制模块，以及与第一AGP总线控制模块通信的第二AGP总线控制模块，经由第二AGP总线与AGP设备通信。 第一和第二AGP总线控制模块的识别码被设置为不显示AGP设备功能，以便允许AGP设备经由扩展适配器与北桥芯片通信。 扩展适配器还包括与PCI设备通信的PCI总线控制模块和用于控制第一AGP总线控制模块和PCI设备之间的数据传输的第一AGP总线控制模块。

公开(公告)号：US20060184757A1

公开(公告)日：2006-08-17

申请号：US11402700

申请日：2006-04-11

申请人： Bi-Yun Yeh ,  Jiin Lai ,  Sheng-Chung Wu

发明人： Bi-Yun Yeh ,  Jiin Lai ,  Sheng-Chung Wu

IPC分类号： G06F13/00

CPC分类号： G06F13/1668 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

摘要： The present invention provides a data memory controller that supports for the invert of data bus. Data transmitted from a memory is received in a chip set, which further transmits the data to a data processing apparatus. While receiving the memory data, the chip set doubles the bandwidth and reduces the frequency, such that the time margin for processing data is increased. In addition, after outputting data to the data processing apparatus, a first frame of data is compared to bus idle state to further reduce frequency of data invert and power consumption.

公开(公告)号：US20050097254A1

公开(公告)日：2005-05-05

申请号：US10980624

申请日：2004-11-03

申请人： Chun-Yuan Su ,  Jiin Lai ,  Chau-Chad Tsai ,  Chi-Che Tsai

发明人： Chun-Yuan Su ,  Jiin Lai ,  Chau-Chad Tsai ,  Chi-Che Tsai

IPC分类号： G06F13/36 ,  G06F13/38

CPC分类号： G06F13/385 ,  G06F2213/0024

摘要： An expansion adapter is used to communicate both PCI and AGP devices to the north bridge chip of a computer. The expansion adapter includes a first AGP bus control module communicable with the north bridge chip via a first AGP bus, and a second AGP bus control module in communication with the first AGP bus control module, communicable with an AGP device via a second AGP bus. The identifying codes of the first and second AGP bus control modules are set to show no AGP device function in order to allow the AGP device to communicate with the north bridge chip via the expansion adapter. The expansion adapter further includes a PCI bus control module in communication with the PCI device and the first AGP bus control module for controlling data transmission between the first AGP bus control module and the PCI device

摘要翻译： 扩展适配器用于将PCI和AGP设备通信到计算机的北桥芯片。 扩展适配器包括经由第一AGP总线与北桥芯片通信的第一AGP总线控制模块，以及与第一AGP总线控制模块通信的第二AGP总线控制模块，经由第二AGP总线与AGP设备通信。 第一和第二AGP总线控制模块的识别码被设置为不显示AGP设备功能，以便允许AGP设备经由扩展适配器与北桥芯片通信。 扩展适配器还包括与PCI设备通信的PCI总线控制模块和用于控制第一AGP总线控制模块和PCI设备之间的数据传输的第一AGP总线控制模块

公开(公告)号：US20050086019A1

公开(公告)日：2005-04-21

申请号：US10904047

申请日：2004-10-21

申请人： Biyun Yeh ,  Victor Wu ,  Jiin Lai

发明人： Biyun Yeh ,  Victor Wu ,  Jiin Lai

IPC分类号： G01R31/28 ,  G01R31/317 ,  G06F19/00 ,  G01R31/00

CPC分类号： G01R31/31725 ,  G01R31/31727

摘要： A method and an apparatus for testing a bridge circuit. The method includes inputting a first test clock to a first conversion unit for triggering the first conversion unit to transfer a test data to a second conversion unit according to rising edges of the first test clock, inputting a second test clock to the second conversion unit for triggering the second conversion unit to output an output data according to falling edges of the second test clock, and controlling the first test clock and the second test clock so that the rising edges of the second test clock are not synchronized to the rising edges of the first test clock. A frequency of the first test clock is an even multiple of a frequency of the second test clock.

摘要翻译： 一种测试桥接电​​路的方法和装置。 该方法包括将第一测试时钟输入到第一转换单元，用于触发第一转换单元根据第一测试时钟的上升沿将测试数据传送到第二转换单元，向第二转换单元输入第二测试时钟 触发所述第二转换单元根据所述第二测试时钟的下降沿输出输出数据，并且控制所述第一测试时钟和所述第二测试时钟，使得所述第二测试时钟的上升沿不与所述第二测试时钟的上升沿同步 第一个测试时钟。 第一测试时钟的频率是第二测试时钟的频率的偶数倍。

公开(公告)号：US06546448B1

公开(公告)日：2003-04-08

申请号：US09440764

申请日：1999-11-16

申请人： Jiin Lai ,  Chau-Chad Tsai ,  Chen-Ping Yang ,  Chi-Che Tsai

发明人： Jiin Lai ,  Chau-Chad Tsai ,  Chen-Ping Yang ,  Chi-Che Tsai

IPC分类号： G06F1314

CPC分类号： G06F13/362

摘要： Method and apparatus for arbitrating access to a pci bus by a plurality of functions in a multi-function master. The arbitrating method is performed among the multiple functions of a multi-function master. The arbiter includes a rotating inquiry scheduler (RIS) and a heuristic inquiry initiator (HII). The RIS receives the local inquiry signal from the functional circuit and stores it. According to the local inquiry signal, a bus inquiry signal is generated and sent to the HII, and is sent to the PCI bus to request a use of the PCI bus. If the PCI bus responds a delay transaction termination, the HII can repeatedly send the bus inquiry signal to the PCI bus until the PCI bus grants the privilege to use the PCI bus. The HII then informs the RIS, which arranges the functional circuit to transmit data through the PCI bus.

摘要翻译： 用于通过多功能主机中的多个功能来仲裁对pci总线的访问的方法和装置。 在多功能主机的多个功能之间执行仲裁方法。 仲裁器包括旋转查询调度程序（RIS）和启发式查询启动器（HII）。 RIS从功能电路接收本地查询信号并存储。 根据本地查询信号，生成总线查询信号并将其发送到HII，并发送到PCI总线以请求使用PCI总线。 如果PCI总线响应延迟事务终止，则HII可以将总线查询信号重复发送到PCI总线，直到PCI总线授予使用PCI总线的权限。 然后，HII通知RIS，该RIS将功能电路通过PCI总线传输数据。

公开(公告)号：US06484281B1

公开(公告)日：2002-11-19

申请号：US09459763

申请日：1999-12-13

申请人： Hsuan-Yi Wang ,  Jiin Lai ,  Nai-Shung Chang

发明人： Hsuan-Yi Wang ,  Jiin Lai ,  Nai-Shung Chang

IPC分类号： G01R3128

CPC分类号： G01R31/318342

摘要： A software-based simulation system is provided, which can provide the combined functionality of a South Bridge test module and a North Bridge test module based solely on either one of the two modules, i.e., either the South Bridge test module or the North Bridge test module without having to use both. This software-based simulation system is characterized in the use of a PCI master modeling circuit and a PCI slave modeling circuit which are capable of simulating the functionality of the North Bridge chipset in the case that only the South Bridge chipset and no North Bridge chipset is included in the simulation system, and are further capable of simulating the functionality of the South Bridge chipset in the case that only the North Bridge chipset and no South Bridge chipset is included in the simulation system.

摘要翻译： 提供了一个基于软件的仿真系统，可以提供南桥测试模块和北桥测试模块的组合功能，该模块仅基于两个模块之一，即南桥测试模块或北桥测试 模块，而不必使用两者。 该基于软件的仿真系统的特征在于使用PCI主建模电路和PCI从属建模电路，其能够模拟北桥芯片组的功能，仅在南桥芯片组和北桥芯片组为 包括在仿真系统中，并且在模拟系统中仅包括北桥芯片组且没有南桥芯片组的情况下，还能够模拟南桥芯片组的功能。