公开(公告)号：US06268748B1

公开(公告)日：2001-07-31

申请号：US09073517

申请日：1998-05-06

申请人： Claude L. Bertin ,  John A. Fifield ,  Russell J. Houghton ,  Christopher P. Miller ,  William R. Tonti

发明人： Claude L. Bertin ,  John A. Fifield ,  Russell J. Houghton ,  Christopher P. Miller ,  William R. Tonti

IPC分类号： G03K19094

CPC分类号： G11C7/1069 ,  G11C7/1051 ,  H03K19/0016 ,  H03K19/09429

摘要： An electronic semiconductor module, either memory or logic, having a driver circuit which includes a multiplicity of driver transistors, together with circuitry for simultaneously applying a first positive bias to a first select number of driver transistors to activate them to an operational state, a second positive bias to a second select number of driver transistors to place them in readiness for activation, and a negative bias to the remaining driver transistors to place them in a fully inactive state thereby reducing noise in the driver circuit. The first positive bias is greater than the transistor threshold voltage, preferably greater than two volts, the second positive bias is less than the threshold voltage, preferably less than one volt, and the negative bias is in the order of minus 0.3 volt. A method of reducing noise in the electronic semiconductor module is also described and includes the applying of a positive bias to a first select number of the transistors to activate them while simultaneously applying a second positive bias to a second select number of the transistors to ready them for activation, and a negative voltage to the remaining transistors to place each in a inactive condition.

摘要翻译： 一种电子半导体模块，无论是存储器还是逻辑，具有包括多个驱动器晶体管的驱动器电路，以及用于同时向第一选择数量的驱动器晶体管施加第一正偏置以将其激活到操作状态的电路，第二 对第二选择数量的驱动器晶体管施加正偏置以使它们准备激活，以及对其余驱动器晶体管的负偏置以将它们置于完全无效状态，从而降低驱动器电路中的噪声。 第一正偏压大于晶体管阈值电压，优选大于2伏，第二正偏压小于阈值电压，优选小于1伏特，负偏压为零下0.3伏。 还描述了降低电子半导体模块中的噪声的方法，并且包括将正偏压施加到第一选择数量的晶体管以激活它们，同时向第二选择数量的晶体管施加第二正偏置以准备它们 用于激活，并且向剩余晶体管施加负电压以使其处于非活动状态。

公开(公告)号：US06177817B1

公开(公告)日：2001-01-23

申请号：US09283960

申请日：1999-04-01

申请人： John A. Fifield ,  Russell J. Houghton ,  Adam B. Wilson

发明人： John A. Fifield ,  Russell J. Houghton ,  Adam B. Wilson

IPC分类号： H03K300

CPC分类号： H03K19/00361 ,  G05F3/242 ,  H03K19/00384

摘要： An off-chip driver circuit with compensated current source including a reference current amplifier and an output driver with a pull-up section. The reference current amplifier includes an input voltage Vcmn from an on chip current reference source. A reference current is established in the reference current amplifier by choosing the Beta of transistor in a current path. A feature of the circuit is that an output current is produced in the output lead of the driver circuit that is proportional to the current in the reference current amplifier, but with adjustments made for the supply voltage level and effective transistor channel length, Leff. Another feature of the circuit is that a reference current-voltage is established on the output lead of the reference current amplifier that is primarily determined by a multiple of the reference current but is reduced by a function of the supply voltage. In the circuit the output current of the driver is reduced linearly and predictably with the supply voltage.

摘要翻译： 具有补偿电流源的片外驱动电路，包括参考电流放大器和具有上拉部分的输出驱动器。 参考电流放大器包括来自片上电流参考源的输入电压Vcmn。 通过在电流通路中选择晶体管的β，在参考电流放大器中建立参考电流。 该电路的一个特征是在驱动电路的输出引线中产生与参考电流放大器中的电流成比例的输出电流，但是对电源电压电平和有效晶体管通道长度Leff进行了调整。 电路的另一个特征是在参考电流放大器的输出引线上建立一个参考电流电压，该参考电流电压主要由参考电流的倍数决定，但是由电源电压的函数所减小。 在电路中，驱动器的输出电流以电源电压线性和可预测地减小。

公开(公告)号：US6127866A

公开(公告)日：2000-10-03

申请号：US239487

申请日：1999-01-28

申请人： Albert M. Chu ,  John A. Fifield ,  Jason E. Rotella ,  Jean-Marc Dortu

发明人： Albert M. Chu ,  John A. Fifield ,  Jason E. Rotella ,  Jean-Marc Dortu

IPC分类号： H03K5/15 ,  G11C7/22 ,  H03L7/081 ,  H03L7/095 ,  H03L7/06

CPC分类号： H03L7/0814 ,  G11C7/22 ,  H03L7/095

摘要： A circuit and method are provided wherein a receiver receives an input train of pulses. The circuit includes a delay-locked-loop coupled to an output of the receiver. The delay-locked-loop includes a pulse generator responsive to received input train of pulses produced at the output of the receiver for producing first pulses in response to the leading edges of the received input train of pulses and second pulses in response to the trailing edges of received input train of pulses. The leading edge of the first pulse has the same edge type as the leading edge of the second pulse (i.e., the leading edge of the first pulse and the leading edge of the second pulse are either both rising edge types or both falling edges types). The first pulses and the second pulses are combined into a composite input signal comprising the first and second pulses with the leading edge of the first pulse maintaining the same edge type. The delay-locked-loop also includes a variable delay line fed by the composite input signal for producing a composite output train of pulses comprising both the first train of pulses and the second train of pulses after a selected time delay provided by the delay line. The delay-locked-loop is responsive to one of the first train of pulses and the second train of pulses in the composite output train of pulses for selecting the time delay of the variable delay line so as to produce the composite output train of pulses with a predetermined phase relationship to the input train of pulses.

摘要翻译： 提供一种电路和方法，其中接收器接收输入的脉冲序列。 电路包括耦合到接收器的输出的延迟锁定环路。 延迟锁定环包括响应于在接收器的输出处产生的接收到的输入脉冲序列的脉冲发生器，以响应于所接收的输入脉冲序列的前沿和响应于后沿的第二脉冲而产生第一脉冲 的接收输入脉冲序列。 第一脉冲的前沿具有与第二脉冲的前沿相同的边缘类型（即，第一脉冲的前沿和第二脉冲的前沿都是上升沿类型或两个下降沿类型） 。 第一脉冲和第二脉冲被组合成包括第一和第二脉冲的复合输入信号，其中第一脉冲的前沿保持相同的边缘类型。 延迟锁定环还包括由复合输入信号馈送的可变延迟线，用于在由延迟线提供的选定时间延迟之后产生包括第一脉冲串和第二脉冲串的两个脉冲的复合输出串。 延迟锁定回路响应于复合输出脉冲串中的第一脉冲序列和第二脉冲串中的一个，用于选择可变延迟线的时间延迟，以便产生具有 与输入的脉冲序列的预定相位关系。

公开(公告)号：US6118318A

公开(公告)日：2000-09-12

申请号：US853963

申请日：1997-05-09

申请人： John A. Fifield ,  Lawrence G. Heller

发明人： John A. Fifield ,  Lawrence G. Heller

IPC分类号： H03K3/3525 ,  H03K3/295 ,  H03K19/0948

CPC分类号： H03K3/3525

摘要： A self biased differential amplifier has a switching point accurately set according to a reference voltage. DC hysteresis is provided, by a circuit internal to the differential amplifier. The amplifier has an input circuit having first and second series connected transistors, wherein the beta ratio of these first and second transistors is changed by enabling an additional transistor of a hysteresis circuit according to an output state of the differential amplifier. When the output state is "high", the switching point is decreased in order that temporary small drops (due to noise or glitches) in the input signal are ignored. Conversely, when the output state is "low", the switching point is increased in order that temporary small increases in the input signal are ignored.

摘要翻译： 自偏置差分放大器具有根据参考电压精确设定的开关点。 通过差分放大器内部的电路提供直流滞后。 放大器具有输入电路，该输入电路具有第一和第二串联连接的晶体管，其中通过根据差分放大器的输出状态启用滞后电路的附加晶体管来改变这些第一和第二晶体管的β比。 当输出状态为“高”时，切换点减小，以便忽略输入信号中的临时小的下降（由于噪声或毛刺）。 相反，当输出状态为“低”时，切换点增加，以便忽略输入信号的临时小的增加。

公开(公告)号：US5757693A

公开(公告)日：1998-05-26

申请号：US803056

申请日：1997-02-19

申请人： Russell J. Houghton ,  Claude L. Bertin ,  John A. Fifield ,  Christopher P. Miller ,  William R. Tonti

发明人： Russell J. Houghton ,  Claude L. Bertin ,  John A. Fifield ,  Christopher P. Miller ,  William R. Tonti

IPC分类号： G11C11/402 ,  G11C11/403 ,  G11C11/405 ,  G11C11/24

CPC分类号： G11C11/405 ,  G11C11/403

摘要： A gain cell in a memory array having read and write bitlines and wordlines, wherein the gain cell comprises a write transistor, a storage node, a read transistor, and a diode is disclosed. The write transistor allows the value of the write bitline to be stored onto the storage node when activated by the write wordline. The read transistor, which allows the stored value to be read, is coupled to the storage node and to the read bitline via the diode. The diode prevents the conduction of the read transistor in the opposite direction, thus preventing read interference from other cells and reducing bitline capacitance.

摘要翻译： 具有读和写位线和字线的存储器阵列中的增益单元，其中增益单元包括写晶体管，存储节点，读晶体管和二极管。 当由写入字线激活时，写入晶体管允许将写入位线的值存储到存储节点上。 允许读取存储值的读取晶体管通过二极管耦合到存储节点和读取位线。 二极管防止读取晶体管在相反方向的导通，从而防止来自其他单元的读取干扰并减少位线电容。

公开(公告)号：US5532622A

公开(公告)日：1996-07-02

申请号：US427396

申请日：1995-04-24

申请人： Mark A. Beiley ,  John A. Fifield

发明人： Mark A. Beiley ,  John A. Fifield

IPC分类号： H03K5/1532 ,  H03K5/1534 ,  H03K19/096

CPC分类号： H03K5/1534

摘要： A transition detector circuit produces an output pulse upon detection of a transition at any one of several input nodes using a single delay path so all input transitions produce the same output pulse width and with only one gate delay in the circuit. The circuit includes precharging means, coupled between the plurality of transitioning inputs and the output node, for charging the output node high. The precharging means comprises stacked field effect transistor (FET) devices, each having a gate connected to a respective one of the transitioning inputs. A first charging device for charging the output node high is coupled to the output node. A second charging device for discharging the output node low is coupled to the output node. A single delay means, coupled between the plurality of transitioning inputs and both the first and second charging devices, both turns off the first charging device and turns on the second charging device. Switching means, controlled by the plurality of transitioning inputs and coupled between the output node and the second charging device, disconnects the second charging device from the output node.

摘要翻译： 当检测到使用单个延迟路径的几个输入节点中的任何一个的转变时，转换检测器电路产生输出脉冲，因此所有输入转换产生相同的输出脉冲宽度，并且在电路中只有一个门延迟。 该电路包括耦合在多个转换输入和输出节点之间的预充电装置，用于对输出节点进行高电压充电。 预充电装置包括堆叠场效应晶体管（FET）器件，每个器件具有连接到相应的一个转换输入的栅极。 用于对输出节点充电的第一充电装置耦合到输出节点。 用于将输出节点放电的第二充电装置耦合到输出节点。 耦合在多个转换输入和第一和第二充电装置之间的单个延迟装置都关闭第一充电装置并打开第二充电装置。 由多个转换输入控制并耦合在输出节点和第二充电装置之间的开关装置将第二充电装置与输出节点断开。

公开(公告)号：USD338541S

公开(公告)日：1993-08-17

申请号：US704638

申请日：1991-05-23

申请人： John A. Fifield

设计人： John A. Fifield

公开(公告)号：US5070671A

公开(公告)日：1991-12-10

申请号：US536591

申请日：1990-06-28

申请人： John A. Fifield ,  Leslie G. Hammond

发明人： John A. Fifield ,  Leslie G. Hammond

IPC分类号： E04D1/04 ,  E04D1/16

CPC分类号： E04D1/04 ,  E04D1/16

摘要： An interlocking roof tile (1) of which the leading end portion (12) at least as far as the lower end of, and including the underlock (6) is tapered in the direction of the leading edge (5) of the tile (1).

摘要翻译： PCT No.PCT / GB89 / 00044 Sec。 371日期1990年6月28日第 102（e）日期1990年6月28日PCT 1989年1月17日PCT PCT。 出版物WO89 / 06728 日期：1989年7月27日。一种互锁屋顶瓦（1），其前端部分（12）至少在下端并且包括锁定件（6）的前端部分（12）沿着前缘 5）。

公开(公告)号：US5022006A

公开(公告)日：1991-06-04

申请号：US175883

申请日：1988-04-01

申请人： John A. Fifield ,  Steven W. Tomashot

发明人： John A. Fifield ,  Steven W. Tomashot

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/84

摘要： A semiconductor memory device is described in which wordline redundancy is implemented without impacting the access time. A redundant decoder circuit generates a wordline drive inhibit signal which inhibits the generation of a normal wordline signal. Deselection also deselects the normally accessed reference cells, requiring that the redundant cells provide their own reference signal. This last requirement is accomplished by utilization of twin cells for the redundant memory. Placing the redundant memory cells on the sense node side of the bit line isolators enables the effective doubling of the number of redundant cells available each of a plurality of sub-arrays of normal memory.

公开(公告)号：US4459609A

公开(公告)日：1984-07-10

申请号：US301563

申请日：1981-09-14

申请人： John A. Fifield ,  Lawrence G. Heller ,  Lloyd A. Walls

发明人： John A. Fifield ,  Lawrence G. Heller ,  Lloyd A. Walls

IPC分类号： G11C11/404 ,  G11C11/56 ,  G11C27/02 ,  H01L29/78 ,  G11C11/24 ,  H01L27/02

CPC分类号： G11C11/404 ,  G11C11/565 ,  G11C27/024 ,  Y10S257/92

摘要： A dense memory is provided which includes a one device random access memory cell using charge fill and spill techniques wherein a potential well under a storage node is filled with charge and the excess charge above a predetermined level is spilled to a diffusion or drain region connected to a sense line through a channel region controlled by pulses on a word line. One bit or two or more bits of information may be stored in the potential well at any given instant of time. Depending upon the value of the increment of voltage applied to the storage node or electrode, a given analog charge packet is stored in a potential well formed under the storage electrode. Information is read by applying a voltage to the word line to turn on the channel region and then stepping down the voltage on the storage electrode in fractional, preferably one half, increments. Charge from a charge packet spilled from the potential well under the storage electrode is detected by a sensing circuit connected to the sense line. To rewrite information into the potential well, the original increment of voltage is applied to the storage node and the sense line is pulled to ground so that the diffusion region acts as a source of charge for the potential well.

摘要翻译： 提供了一种密集存储器，其包括使用电荷填充和溢出技术的一个器件随机存取存储器单元，其中存储节点下方的势阱填充有电荷，并且超过预定水平的超量电荷溢出到连接到 通过由字线上的脉冲控制的通道区域的感测线。 信息的一位或两位或更多位可以在任何给定的时刻存储在潜在井中。 取决于施加到存储节点或电极的电压增量的值，给定的模拟电荷包被存储在形成在存储电极下方的势阱中。 通过向字线施加电压来读取信息以打开通道区域，然后以分数，优选为一半的增量降低存储电极上的电压。 通过连接到感测线的感测电路来检测从存储电极下方的电位阱溢出的电荷分组的充电。 为了将信息重写到势阱中，电压的原始增量被施加到存储节点，并且感测线被拉到地，使得扩散区充当势阱的电荷源。