公开(公告)号：US5260952A

公开(公告)日：1993-11-09

申请号：US693509

申请日：1991-04-30

申请人： Kenneth E. Beilstein, Jr. ,  John A. Fifield ,  Lawrence G. Heller ,  Hsing-San Lee ,  Charles H. Stapper

发明人： Kenneth E. Beilstein, Jr. ,  John A. Fifield ,  Lawrence G. Heller ,  Hsing-San Lee ,  Charles H. Stapper

IPC分类号： G01R31/317 ,  G06F11/08 ,  G06F11/10 ,  G06F11/16 ,  G11C29/00 ,  H03K19/00 ,  H03K19/003 ,  G01K31/28

CPC分类号： H03K19/00392 ,  G06F11/1044 ,  G11C29/84

摘要： A logic system including a first logic block for providing first differential outputs; a second logic block, identical to the first logic block, for providing second differential outputs; a fault detecting device, coupled to the first logic block, for detecting a fault in the first differential outputs; and a selecting device, coupled to the first and second logic blocks and to the fault detecting device, for selecting an output of one of the first and second logic blocks depending on whether the fault detecting device detects a fault.

摘要翻译： 一种逻辑系统，包括用于提供第一差分输出的第一逻辑块; 第二逻辑块，与第一逻辑块相同，用于提供第二差分输出; 耦合到第一逻辑块的故障检测装置，用于检测第一差分输出中的故障; 以及耦合到第一和第二逻辑块和故障检测装置的选择装置，用于根据故障检测装置是否检测到故障来选择第一和第二逻辑块之一的输出。

公开(公告)号：US6118318A

公开(公告)日：2000-09-12

申请号：US853963

申请日：1997-05-09

申请人： John A. Fifield ,  Lawrence G. Heller

发明人： John A. Fifield ,  Lawrence G. Heller

IPC分类号： H03K3/3525 ,  H03K3/295 ,  H03K19/0948

CPC分类号： H03K3/3525

摘要： A self biased differential amplifier has a switching point accurately set according to a reference voltage. DC hysteresis is provided, by a circuit internal to the differential amplifier. The amplifier has an input circuit having first and second series connected transistors, wherein the beta ratio of these first and second transistors is changed by enabling an additional transistor of a hysteresis circuit according to an output state of the differential amplifier. When the output state is "high", the switching point is decreased in order that temporary small drops (due to noise or glitches) in the input signal are ignored. Conversely, when the output state is "low", the switching point is increased in order that temporary small increases in the input signal are ignored.

摘要翻译： 自偏置差分放大器具有根据参考电压精确设定的开关点。 通过差分放大器内部的电路提供直流滞后。 放大器具有输入电路，该输入电路具有第一和第二串联连接的晶体管，其中通过根据差分放大器的输出状态启用滞后电路的附加晶体管来改变这些第一和第二晶体管的β比。 当输出状态为“高”时，切换点减小，以便忽略输入信号中的临时小的下降（由于噪声或毛刺）。 相反，当输出状态为“低”时，切换点增加，以便忽略输入信号的临时小的增加。

公开(公告)号：US4459609A

公开(公告)日：1984-07-10

申请号：US301563

申请日：1981-09-14

申请人： John A. Fifield ,  Lawrence G. Heller ,  Lloyd A. Walls

发明人： John A. Fifield ,  Lawrence G. Heller ,  Lloyd A. Walls

IPC分类号： G11C11/404 ,  G11C11/56 ,  G11C27/02 ,  H01L29/78 ,  G11C11/24 ,  H01L27/02

CPC分类号： G11C11/404 ,  G11C11/565 ,  G11C27/024 ,  Y10S257/92

摘要： A dense memory is provided which includes a one device random access memory cell using charge fill and spill techniques wherein a potential well under a storage node is filled with charge and the excess charge above a predetermined level is spilled to a diffusion or drain region connected to a sense line through a channel region controlled by pulses on a word line. One bit or two or more bits of information may be stored in the potential well at any given instant of time. Depending upon the value of the increment of voltage applied to the storage node or electrode, a given analog charge packet is stored in a potential well formed under the storage electrode. Information is read by applying a voltage to the word line to turn on the channel region and then stepping down the voltage on the storage electrode in fractional, preferably one half, increments. Charge from a charge packet spilled from the potential well under the storage electrode is detected by a sensing circuit connected to the sense line. To rewrite information into the potential well, the original increment of voltage is applied to the storage node and the sense line is pulled to ground so that the diffusion region acts as a source of charge for the potential well.

摘要翻译： 提供了一种密集存储器，其包括使用电荷填充和溢出技术的一个器件随机存取存储器单元，其中存储节点下方的势阱填充有电荷，并且超过预定水平的超量电荷溢出到连接到 通过由字线上的脉冲控制的通道区域的感测线。 信息的一位或两位或更多位可以在任何给定的时刻存储在潜在井中。 取决于施加到存储节点或电极的电压增量的值，给定的模拟电荷包被存储在形成在存储电极下方的势阱中。 通过向字线施加电压来读取信息以打开通道区域，然后以分数，优选为一半的增量降低存储电极上的电压。 通过连接到感测线的感测电路来检测从存储电极下方的电位阱溢出的电荷分组的充电。 为了将信息重写到势阱中，电压的原始增量被施加到存储节点，并且感测线被拉到地，使得扩散区充当势阱的电荷源。

公开(公告)号：US5550488A

公开(公告)日：1996-08-27

申请号：US466904

申请日：1995-06-06

申请人： John A. Fifield ,  Lawrence G. Heller

发明人： John A. Fifield ,  Lawrence G. Heller

IPC分类号： H03K19/094 ,  H03K19/096 ,  H03K19/00 ,  H03K19/02

CPC分类号： H03K19/09429 ,  H03K19/0966

摘要： A self-timed tri-state driver circuit for a dual-rail differential input and single-ended output is disclosed. The circuit generates a tri-state mode in response to an Output Enable (OE) input pulsing low. The OE signal input is driven high to place the driver circuit into a ready state. The circuit is maintained in a tri-state mode until data appears at the inputs. Once a data signal is received after the tri-state circuit is in the ready state, the output immediately outputs this signal. Therefore, the output of the driver is self-timed from the arrival of the data.

摘要翻译： 公开了一种用于双轨差分输入和单端输出的自定时三态驱动电路。 电路响应于输出使能（OE）输入脉冲为低电平产生三态模式。 OE信号输入被驱动为高电平，以将驱动电路置于就绪状态。 电路保持三态模式，直到数据出现在输入端。 一旦在三态电路处于就绪状态之后接收到数据信号，输出立即输出该信号。 因此，驱动程序的输出是从数据到达时自动进行的。

公开(公告)号：US4300210A

公开(公告)日：1981-11-10

申请号：US108242

申请日：1979-12-27

申请人： Satya N. Chakravarti ,  Lawrence G. Heller ,  Wilbur D. Pricer

发明人： Satya N. Chakravarti ,  Lawrence G. Heller ,  Wilbur D. Pricer

IPC分类号： G11C11/409 ,  G11C11/4091 ,  G11C11/56 ,  G11C19/36 ,  H03K5/08 ,  G11C27/00 ,  G11C11/24 ,  G11C11/40

CPC分类号： G11C11/565 ,  G11C11/4091 ,  G11C19/36 ,  G11C7/06

摘要： A calibrated sensing system is provided in accordance with the teachings of this invention for sensing charge in a storage medium, such as a storage capacitor, coupled to an access or bit/sense line which compensates for most sources of variability in the storage medium and in the access line. In the system, the unknown charge stored in the storage medium is transferred to a first capacitor or potential well via the access line. A high charge state of the storage medium is written into the storage medium and known fractional packets of charge are prepared therefrom, transferred selectively to a second capacitor or potential well and compared with the unknown charge in the first potential to determine the relative level of the unknown charge that was stored in the storage medium. By selectively using two or more fractional packets of charge multilevel sensing is performed.

摘要翻译： 根据本发明的教导，提供了一种校准的感测系统，用于感测存储介质（例如存储电容器）中的电荷，该存储介质耦合到访问或位/检测线，其补偿存储介质中的大部分变异源，并且 接入线路。 在系统中，存储在存储介质中的未知电荷经由存取线路传送到第一电容器或势阱。 将存储介质的高电荷状态写入存储介质，并且从其准备已知的分数电荷分组，将其选择性地传输到第二电容器或势阱，并与第一电位中的未知电荷进行比较，以确定第 存储在存储介质中的未知电荷。 通过选择性地使用两个或更多个电荷多级感测的分数分组。

公开(公告)号：US4137464A

公开(公告)日：1979-01-30

申请号：US825016

申请日：1977-08-16

申请人： Lawrence G. Heller ,  Lewis M. Terman

发明人： Lawrence G. Heller ,  Lewis M. Terman

IPC分类号： H03M1/44 ,  G11C11/56 ,  G11C19/18 ,  G11C19/36 ,  G11C27/02 ,  H03K4/02 ,  H03M1/00 ,  H03M1/66

CPC分类号： G11C27/024 ,  G11C19/186 ,  G11C19/36 ,  H03M1/804

摘要： A bucket brigade circuit is described for generating a sequence of packets of charge carriers of the form Q.sub.R /2, Q.sub.R /4, Q.sub.R /8....Q.sub.R /2.sup.N where N is an integer. The charge packets thus generated can be employed in combinations in either digital-to-analog or analog-to-digital converters. The charge generation circuit requires two equal capacitors which are used for charge redistribution. To obtain accurate quantities of charge in the generated charge packets the capacitors employed should be large, however the use of large capacitors results in low operating speed because of the large charge transfer time constants involved. The described circuit provides a scheme to reduce charge transfer time constants and therefore obtain greater speed while still permitting the use of large capacitors for high accuracy. The circuit includes a small coupling capacitor connected in series with one of the charge redistribution capacitors to produce a total capacitance which is equal to or smaller than the coupling capacitance. The sequence of charge carriers produced by the circuit can be injected into either a bucket brigade circuit or a charge-coupled-device circuit for use, for example, in digital-to-analog and analog-to-digital converters.

摘要翻译： 描述了用于产生形式为QR / 2，QR / 4，QR / 8 .... QR / 2N的电荷载体的序列序列的桶旅电路，其中N是整数。 这样产生的电荷包可以以数模转换器或模数转换器的组合使用。 电荷产生电路需要用于电荷再分配的两个相等的电容器。 为了在产生的电荷包中获得准确的电荷量，所使用的电容应该是大的，然而由于涉及大的电荷转移时间常数，使用大的电容器导致低的操作速度。 所描述的电路提供了一种减少电荷转移时间常数并因此获得更高速度同时允许使用大电容器以获得高精度的方案。 电路包括与电荷再分配电容器中的一个串联连接的小耦合电容器，以产生等于或小于耦合电容的总电容。 由电路产生的电荷载体的序列可以被注入到例如在数模转换器和模数转换器中使用的桶式电路或电荷耦合器件电路中。

公开(公告)号：US4591993A

公开(公告)日：1986-05-27

申请号：US554148

申请日：1983-11-21

申请人： William R. Griffin ,  Lawrence G. Heller

发明人： William R. Griffin ,  Lawrence G. Heller

IPC分类号： H01L21/8238 ,  H01L21/82 ,  H01L27/092 ,  H01L27/112 ,  H01L27/118 ,  H03K19/0948 ,  H03K19/173 ,  H03K19/094

CPC分类号： H03K19/0948 ,  H01L27/112

摘要： A methodology is provided for reducing an arbitrary Boolean logic expression to static CMOS circuits by the use of a general matrix of P channel devices and N channel devices which are interconnected in accordance with the terms of Boolean logic expressions derived from a truth table. More specifically, from a Boolean expression a sum-of-products expression giving the 1 binary data outputs of a truth table having a 0 input is found. This is accomplished by complementing, or barring, the literals which are a binary 1 when the output is 1 and leaving true or unbarred the literals that are a binary 0. Then each input of a given product term is applied to the control gate of a P channel device, which devices are connected in series with one end tied to a source of potential and the other end of the series circuit connected to an output terminal. Each product term is arranged in parallel with other P channel device series circuits to form one half of a complete logic matrix. Similarly, for the other half of the matrix, a sum-of-products expression giving the binary 0 outputs of a truth table having a binary 1 for an input is found. Each input of a given product term is applied to the control gate of an N channel device, which devices are connected in series with one end tied to a potential reference point, such as ground, and the other end of the series circuit is connected to the output terminal. Each product term is arranged in parallel with other N channel device series circuits.

摘要翻译： 提供了一种通过使用根据从真值表导出的布尔逻辑表达式的术语互连的P通道器件和N沟道器件的通用矩阵来将静态CMOS电路的任意布尔逻辑表达式减少的方法。 更具体地，从布尔表达式中，找到给出具有0输入的真值表的1个二进制数据输出的乘积和表达式表达式。 这是通过补充或限制当输出为1时为二进制1的文字，并将真实的或未被标记为二进制0的文字来实现的。然后，将给定产品项的每个输入应用于 P通道器件，这些器件串联连接到电位源的一端，串联电路的另一端连接到输出端子。 每个产品术语与其他P通道器件串联电路并联布置，形成完整逻辑矩阵的一半。 类似地，对于矩阵的另一半，找到给出用于输入的具有二进制1的真值表的二进制0输出的乘积和表达式。 给定产品项的每个输入被施加到N沟道器件的控制栅极，这些器件与连接到诸如地的参考点的一端串联连接，串联电路的另一端连接到 输出端子。 每个产品术语与其他N通道器件串联电路并联布置。

公开(公告)号：US4288864A

公开(公告)日：1981-09-08

申请号：US087843

申请日：1979-10-24

申请人： Thomas V. Harroun ,  Lawrence G. Heller ,  Norbert G. Vogl, Jr.

发明人： Thomas V. Harroun ,  Lawrence G. Heller ,  Norbert G. Vogl, Jr.

IPC分类号： G11C27/04 ,  G11C19/28 ,  H01L21/339 ,  H01L27/105 ,  H01L29/762 ,  G11C11/40

CPC分类号： G11C19/287 ,  H01L27/1057

摘要： An SPS CCD memory system is provided wherein a single tap, preferably a storage node, on an input serial or shift register is connected to the input of a plurality of parallel shift registers through a fan out circuit and the output of the plurality of parallel shift registers is connected to a single tap, preferably a storage node, on an output serial or shift register through a fan in circuit.

摘要翻译： 提供了一种SPS CCD存储器系统，其中在输入串行或移位寄存器上的单个抽头，优选地存储节点通过扇出电路连接到多个并行移位寄存器的输入，并且多个并行移位的输出 寄存器通过电路中的风扇连接到输出串行或移位寄存器上的单个抽头，最好是存储节点。

公开(公告)号：US5831452A

公开(公告)日：1998-11-03

申请号：US803582

申请日：1997-02-20

申请人： Edward Joseph Nowak ,  Minh Ho Tong ,  Lawrence G. Heller

发明人： Edward Joseph Nowak ,  Minh Ho Tong ,  Lawrence G. Heller

IPC分类号： H03K19/096 ,  H03K19/0948

CPC分类号： H03K19/0963

摘要： A novel precharge circuit is provided for dynamic CMOS logic circuits which are immune to leakage currents and reduce overall power consumption. The circuit comprises a precharge transistor for precharging a node to a high voltage level indicting a first logic state during a standby mode. Thereafter, during an active mode, the node may or may not be discharged by connected logic circuitry. If the node is discharged, then an additional transistor is provided to inhibit the precharging of the already charged node during a subsequent standby mode. Similarly, if the node is not discharged, a small keeper transistor is provided to keep the node at a fully precharged level.

摘要翻译： 为动态CMOS逻辑电路提供了一种新颖的预充电电路，其免于漏电流并降低总体功耗。 电路包括用于在待机模式期间将节点预充电到指示第一逻辑状态的高电压电平的预充电晶体管。 此后，在活动模式期间，节点可以被连接的逻辑电路放电，也可以不被放电。 如果节点放电，则提供附加晶体管以在随后的待机模式期间禁止已经充电的节点的预充电。 类似地，如果节点不被放电，则提供小的保持晶体管以保持节点处于完全预充电电平。

公开(公告)号：US4638482A

公开(公告)日：1987-01-20

申请号：US685880

申请日：1984-12-24

申请人： William R. Griffin ,  Lawrence G. Heller ,  Peter N. Horowitz

发明人： William R. Griffin ,  Lawrence G. Heller ,  Peter N. Horowitz

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G06F11/0751

摘要： A system for testing a differential logic network is provided which includes a differential exclusive OR circuit having a plurality of inputs for receiving complementary signals from the differential logic network and first and second output terminals and means, e.g., a conventional exclusive OR circuit, for determining the voltage difference between the first and second output terminals to indicate the presence or absence of a fault or error in the differential logic network under test.

摘要翻译： 提供了一种用于测试差分逻辑网络的系统，其包括具有多个输入的差分异或电路，用于从差分逻辑网络和第一和第二输出端子接收互补信号，以及用于确定 第一和第二输出端子之间的电压差，以指示被测差分逻辑网络中存在或不存在故障或错误。