利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

266 条记录 (耗时 0.03 秒)

    MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION
    61.
    发明申请
    MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION 有权
    多级存储单元利用测量时间延迟作为等级定义的特征参数

    公开(公告)号：US20090073783A1

    公开(公告)日：2009-03-19

    申请号：US11857321

    申请日：2007-09-18

    申请人： Matthew J. Breitwisch ,  Chung H. Lam ,  Bipin Rajendran

    发明人： Matthew J. Breitwisch ,  Chung H. Lam ,  Bipin Rajendran

    IPC分类号： G11C7/00 ,  G11C7/10

    CPC分类号： G11C13/0061 ,  G11C11/5628 ,  G11C11/565 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/32 ,  G11C2013/0054

    摘要： A memory array and computer program product for operating a memory cell and memory array. An embodiment of the invention entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell to a pre-charge voltage. A word-line in the electronic circuit is then activated. A discharging operation discharges the bit-line capacitor through the said memory cell in the electronic circuit to the word-line. Additionally, an electron discharge time measurement is started when the word-line is activated. The electron discharge time measurement is stopped when the voltage level in the bit-line falls below a pre-defined reference voltage. A determining operation determines the binary value from the measured electron discharge time.

    摘要翻译： 用于操作存储器单元和存储器阵列的存储器阵列和计算机程序产品。 本发明的实施例需要接收读取存储在存储单元中的二进制值的请求。 预充电操作将由存储器单元形成的电子电路中的位线电容器预先充电到预充电电压。 然后激活电子电路中的字线。 放电操作通过电子电路中的所述存储单元将位线电容器放电到字线。 此外，当字线被激活时，电子放电时间测量开始。 当位线中的电压电平低于预定义的参考电压时，停止电子放电时间测量。 确定操作根据测量的电子放电时间确定二进制值。

    Measurement method for reading multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition
    62.
    发明授权
    Measurement method for reading multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition 失效
    使用测量时间延迟读取多级存储单元作为电平定义的特征参数的测量方法

    公开(公告)号：US07505334B1

    公开(公告)日：2009-03-17

    申请号：US12128291

    申请日：2008-05-28

    申请人： Matthew J. Breitwisch ,  Chung H. Lam ,  Bipin Rajendran

    发明人： Matthew J. Breitwisch ,  Chung H. Lam ,  Bipin Rajendran

    IPC分类号： G11C7/06 ,  G11C7/08 ,  G11C16/26 ,  G11C11/4197 ,  G11C11/4193 ,  G11C16/06

    CPC分类号： G11C13/004 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0061 ,  G11C16/32 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2211/5634

    摘要： A method for operating a memory cell in which a variation of the characteristic parameter of the memory cell affects the effective resistance of the memory cell. The method includes measuring a first discharge time of a reference voltage through the memory cell, determining that the first discharge time is less than a minimum discharge time, adding a supplemental capacitor in parallel with the memory cell, adding including coupling the capacitor to the memory cell through a switch, measuring a second discharge time of the reference voltage through the memory cell, storing the second discharge time and determining the value stored in the memory cell based on the second discharge time. Measuring the first and second discharge times includes pre-charging an electronic circuit coupled to the memory cell, activating the memory cell so as to discharge the electronic circuit, at least partially through the memory cell, starting a time measurement when the memory cell is activated, and stopping the time measurement when the voltage level in the electronic circuit falls below a pre-defined reference voltage.

    摘要翻译： 一种用于操作存储单元的特性参数的变化影响存储单元的有效电阻的存储单元的方法。 该方法包括测量通过存储器单元的参考电压的第一放电时间，确定第一放电时间小于最小放电时间，将补充电容器与存储器单元并联，增加包括将电容器耦合到存储器 通过开关测量参考电压的第二放电时间，存储第二放电时间，并基于第二放电时间确定存储在存储器单元中的值。 测量第一和第二放电时间包括对连接到存储器单元的电子电路进行预充电，激活存储器单元以至少部分地通过存储器单元对电子电路进行放电，当存储器单元被激活时启动时间测量 并且当电子电路中的电压电平低于预定义的参考电压时停止时间测量。

    Fin-type antifuse
    63.
    发明授权
    Fin-type antifuse 有权
    翅式反熔丝

    公开(公告)号：US07456426B2

    公开(公告)日：2008-11-25

    申请号：US10711845

    申请日：2004-10-08

    申请人： Mathew J. Breitwisch ,  Chung H. Lam ,  Edward J. Nowak

    发明人： Mathew J. Breitwisch ,  Chung H. Lam ,  Edward J. Nowak

    IPC分类号： H01L29/04 ,  H01L31/036

    CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A method of forming an antifuse forms a material layer and then patterns the material layer into a fin. The center portion of the fin is converted into a substantially non-conductive region and the end portions of the fin into conductors. The process of converting the center portion of the fin into an insulator allows a process of heating the fin above a predetermined temperature to convert the insulator into a conductor. Thus, the fin-type structure that can be selectively converted from an insulator into a permanent conductor using a heating process.

    摘要翻译： 形成反熔丝的方法形成材料层，然后将材料层图案化成翅片。 翅片的中心部分被转换成基本上不导电的区域，并且翅片的端部变成导体。 将翅片的中心部分转换成绝缘体的过程允许将翅片加热到高于预定温度的过程，以将绝缘体转换为导体。 因此，可以使用加热工艺从绝缘体选择性地转换成永久导体的鳍式结构。

    ON-CHIP ELECTRICALLY ALTERABLE RESISTOR
    64.
    发明申请
    ON-CHIP ELECTRICALLY ALTERABLE RESISTOR 有权
    片上电可更换电阻

    公开(公告)号：US20080186071A1

    公开(公告)日：2008-08-07

    申请号：US12060889

    申请日：2008-04-02

    申请人： Louis C. Hsu ,  Brian L. Ji ,  Chung H. Lam

    发明人： Louis C. Hsu ,  Brian L. Ji ,  Chung H. Lam

    IPC分类号： H03H11/26

    CPC分类号： H03H11/24

    摘要： A programmable, electrically alterable (EA) resistor, an integrated circuit (IC) chip including the EA resistor and integrated analog circuits using on-chip EA resistors. Phase change storage media form resistors (EA resistors) on an IC that may be formed in an array of parallel EA resistors to set variable circuit bias conditions for circuits on the IC and in particular, bias on-chip analog circuits. The bias resistance is changed by changing EA resistor phase. Parallel connection of the parallel EA resistors may be dynamically alterable, switching one or more parallel resistors in and out digitally.

    摘要翻译： 一个可编程的，电气可变的（EA）电阻器，集成电路（IC）芯片，其中包括EA电阻器和使用片上EA电阻器的集成模拟电路。 相变存储介质在IC上形成电阻器（EA电阻器），其可以形成在并联EA电阻器阵列中，以设置IC上的电路的可变电路偏置条件，特别是片上模拟电路偏置。 通过改变EA电阻相位来改变偏置电阻。 并联EA电阻器的并联连接可以是动态可变的，以数字方式切换一个或多个并联电阻器。

    Simultaneous Conditioning of a Plurality of Memory Cells Through Series Resistors
    65.
    发明申请
    Simultaneous Conditioning of a Plurality of Memory Cells Through Series Resistors 有权
    通过串联电阻同时调节多个存储单元

    公开(公告)号：US20080185652A1

    公开(公告)日：2008-08-07

    申请号：US12060922

    申请日：2008-04-02

    申请人： Toshijaru Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger ,  Chung H. Lam ,  Gerhard I. Meijer

    发明人： Toshijaru Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger ,  Chung H. Lam ,  Gerhard I. Meijer

    IPC分类号： H01L23/62 ,  H01L21/8234

    CPC分类号： H01L27/0629 ,  H01L27/101 ,  H01L27/24

    摘要： Disclosed are a semiconductor structure and a method that allow for simultaneous voltage/current conditioning of multiple memory elements in a nonvolatile memory device with multiple memory cells. The structure and method incorporate the use of a resistor connected in series with the memory elements to limit current passing through the memory elements. Specifically, the method and structure incorporate a blanket temporary series resistor on the wafer surface above the memory cells and/or permanent series resistors within the memory cells. During the conditioning process, these resistors protect the transition metal oxide in the individual memory elements from damage (i.e., burn-out), once it has been conditioned.

    摘要翻译： 公开了一种半导体结构和方法，其允许在具有多个存储器单元的非易失性存储器件中同时对多个存储器元件进行电压/电流调节。 该结构和方法结合使用与存储器元件串联连接的电阻器来限制电流通过存储器元件。 具体地，该方法和结构在存储器单元上方的晶片表面上和/或存储器单元内的永久串联电阻器上并入一个橡皮布暂时串联电阻器。 在调节过程中，一旦调节了这些电阻，这些电阻就可以保护各个存储元件中的过渡金属氧化物免受损坏（即烧坏）。

    MAXIMUM LIKELIHOOD STATISTICAL METHOD OF OPERATIONS FOR MULTI-BIT SEMICONDUCTOR MEMORY
    66.
    发明申请
    MAXIMUM LIKELIHOOD STATISTICAL METHOD OF OPERATIONS FOR MULTI-BIT SEMICONDUCTOR MEMORY 失效
    用于多位半导体存储器的最大似然统计运算方法

    公开(公告)号：US20080165595A1

    公开(公告)日：2008-07-10

    申请号：US11620704

    申请日：2007-01-07

    申请人： Chung H. Lam

    发明人： Chung H. Lam

    IPC分类号： G11C7/00

    CPC分类号： G11C11/5628 ,  G11C7/16 ,  G11C11/56 ,  G11C11/5642 ,  G11C16/3418 ,  G11C16/3431 ,  G11C27/005 ,  G11C2211/5641

    摘要： An operating procedure to provide a cost effective method to maximize the number of levels with respect to a characteristic parameter of a memory cell. The procedures utilize statistical analysis to determine the most likely binary value associated with the characteristic parameter value. In one embodiment, a receiving unit reads the values of the characteristic parameter for each memory cell in the memory cell collection containing a target memory cell. A generating unit generates a probability distribution function of the characteristic parameter for each of the possible binary values for the memory cell collection. The generating unit uses the probability distribution function to determine the probable value range for the shifted value of the characteristic parameter of the target memory cell. The value of the characteristic parameter for the target memory cell is converted into a binary value for which the probability is highest.

    摘要翻译： 提供一种成本有效的方法以使相对于存储器单元的特征参数的级数最大化的操作程序。 该程序利用统计分析来确定与特征参数值相关的最可能的二进制值。 在一个实施例中，接收单元读取包含目标存储器单元的存储单元集合中的​​每个存储器单元的特性参数的值。 生成单元生成用于存储单元集合的每个可能二进制值的特性参数的概率分布函数。 生成单元使用概率分布函数来确定目标存储单元的特征参数的移位值的可能值范围。 目标存储器单元的特性参数的值被转换成概率最高的二进制值。

    UNIFORM CRITICAL DIMENSION SIZE PORE FOR PCRAM APPLICATION
    67.
    发明申请
    UNIFORM CRITICAL DIMENSION SIZE PORE FOR PCRAM APPLICATION 审中-公开
    用于PCRAM应用的均匀尺寸尺寸孔

    公开(公告)号：US20080164453A1

    公开(公告)日：2008-07-10

    申请号：US11620671

    申请日：2007-01-07

    申请人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Chung H. Lam ,  Hsiang-Lan Lung ,  Eirc A. Joseph ,  Alejandro G. Schrott

    发明人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Chung H. Lam ,  Hsiang-Lan Lung ,  Eirc A. Joseph ,  Alejandro G. Schrott

    IPC分类号： H01L47/00 ,  H01L21/28

    CPC分类号： H01L45/1683 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148

    摘要： A memory cell and a method of making the same, that includes insulating material deposited on a substrate, a bottom electrode formed within the insulating material, a plurality of insulating layers deposited above the bottom electrode and at least one of which acts as an intermediate insulating layer. A via is defined in the insulating layers above the intermediate insulating layer. A channel is created for etch with a sacrificial spacer. A pore is defined in the intermediate insulating layer. All insulating layers above the intermediate insulating layer are removed, and the entirety of the remaining pore is filled with phase change material. An upper electrode is formed above the phase change material.

    摘要翻译： 存储单元及其制造方法，其包括沉积在基板上的绝缘材料，形成在绝缘材料内的底部电极，沉积在底部电极上方的多个绝缘层，并且其中至少一个用作中间绝缘层 层。 在中间绝缘层上方的绝缘层中限定通孔。 创建一个通道用于用牺牲隔离物进行蚀刻。 在中间绝缘层中限定孔。 除去中间绝缘层之上的所有绝缘层，并且剩余的孔的整个填充有相变材料。 在相变材料上形成上电极。