Scalable synchronous packet transmit scheduler
    61.
    发明授权
    Scalable synchronous packet transmit scheduler 失效
    可扩展同步分组传输调度器

    公开(公告)号:US07756100B2

    公开(公告)日:2010-07-13

    申请号:US11612468

    申请日:2006-12-18

    Inventor: John Lin Paris Chen

    CPC classification number: H04W72/1242

    Abstract: A baseband controller system creates and maintains a schedule of synchronized events and reviews the schedule as a part of determining whether to initiate a transmission of a non-synchronous event (one that is not time sensitive, for example, e-mail). One aspect of the present invention is to create a system and method that avoids a possibility of collision between synchronized and non-synchronized communication events. A synchronized event is a scheduled transmission of time sensitive data such as what is often known as continuous bit rate data. Examples include video and voice wherein a collision (inability to transmit the continuous bit rate data) may result in degradation of signal quality at the receiving end. The inventive system and method evaluate the schedule of synchronized events in relation to the present time and determine whether a non-synchronized event may be transmitted without the likelihood of a collision. Making the determination that such a transmission may occur includes evaluating future time periods to see if a synchronized event is scheduled during a time period in which the non-synchronized event would continue to be transmitted for those non-synchronized events that span two or more defined time periods in length.

    Abstract translation: 基带控制器系统创建并维护同步事件的调度并且将该调度作为确定是否发起非同步事件(不是时间敏感的事件(例如,电子邮件))的一部分来审查。 本发明的一个方面是创建一种避免同步和非同步通信事件之间的冲突的可能性的系统和方法。 同步事件是时间敏感数据的预定传输,例如通常称为连续比特率数据。 其中碰撞(不能发送连续比特率数据)的视频和语音可能导致接收端的信号质量下降。 本发明的系统和方法评估与当前时间相关的同步事件的调度,并且确定是否可以在没有碰撞的可能性的情况下发送非同步事件。 确定可能发生这种传输包括评估未来时间段以查看是否在在跨越两个或更多个定义的那些非同步事件的情况下继续发送非同步事件的时间段期间调度同步事件 时间长度。

    Method to manufacture LDMOS transistors with improved threshold voltage control
    62.
    发明授权
    Method to manufacture LDMOS transistors with improved threshold voltage control 有权
    用改进的阈值电压控制制造LDMOS晶体管的方法

    公开(公告)号:US07696049B2

    公开(公告)日:2010-04-13

    申请号:US11552198

    申请日:2006-10-24

    Abstract: A double diffused region (65), (75), (85) is formed in a semiconductor substrate or in an epitaxial layer (20) formed on the semiconductor substrate. The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to the hard bake process, a heavy implant species such as arsenic is implanted into the epitaxial layer. During subsequent processing, such as during LOCOS formation, a double diffused region is formed by a thermal anneal. A dielectric layer (120) is formed on the epitaxial layer (20) and gate structures (130), (135) are formed over the dielectric layer (120).

    Abstract translation: 在半导体衬底或形成在半导体衬底上的外延层(20)中形成双扩散区域(65),(75),(85)。 通过在硬烘烤过程之前首先将诸如硼的光注入物质在光致抗蚀剂层中的开口注入,形成双扩散区域。 在硬烘烤过程之后,将诸如砷的重注入物质注入到外延层中。 在后续处理中,例如在LOCOS形成期间,通过热退火形成双扩散区域。 在外延层(20)上形成介电层(120),并且在电介质层(120)之上形成栅极结构(130),(135)。

    Packetized audio data operations in a wireless local area network device
    63.
    发明授权
    Packetized audio data operations in a wireless local area network device 有权
    无线局域网设备中的分组化音频数据操作

    公开(公告)号:US07684377B2

    公开(公告)日:2010-03-23

    申请号:US12174629

    申请日:2008-07-16

    CPC classification number: H04W88/06 H04W28/14 H04W84/12

    Abstract: A wireless local area network (WLAN) transceiving integrated circuit includes a WLAN interface, an input buffer, an input buffer controller, and a processor. The WLAN transceiving integrated circuit may also include an output buffer, an output buffer controller, a transcoder, and/or an audio Coder-Decoder (CODEC). The WLAN transceiving integrated circuit is installed in a WLAN device that services voice communications. The input buffer receives packetized audio data from the WLAN interface. When the input buffer satisfies a buffer vacancy threshold, the processor and the input buffer controller cooperatively operate to fill at least a portion of the input buffer with packetized audio data. The processor copies packetized audio data from the input buffer and fills the input buffer with the copied packetized audio data to maintain an audio pattern in the input buffer. The input buffer controller fills the input buffer when the processor is available and after copying/filling is no longer effective. The processor operates to maintain the audio pattern when additional packetized audio data is received by the WLAN interface. These operations are also performed for the output buffer, which receives packetized audio data from the transcoder and writes the packetized audio data to the WLAN interface.

    Abstract translation: 无线局域网(WLAN)收发集成电路包括WLAN接口,输入缓冲器,输入缓冲器控制器和处理器。 WLAN收发集成电路还可以包括输出缓冲器,输出缓冲器控制器,代码转换器和/或音频编解码器(CODEC)。 WLAN收发集成电路安装在服务语音通信的WLAN设备中。 输入缓冲区从WLAN接口接收分组化音频数据。 当输入缓冲器满足缓冲空缺阈值时,处理器和输入缓冲器控制器协同工作,以便用分组化音频数据填充输入缓冲器的至少一部分。 处理器从输入缓冲器复制分组化的音频数据,并用复制的分组化音频数据填充输入缓冲器,以保持输入缓冲器中的音频模式。 当处理器可用并且复制/填充不再有效之后,输入缓冲器控制器填充输入缓冲器。 当附加的分组化音频数据被WLAN接口接收时,处理器操作以维持音频模式。 这些操作也对输出缓冲器执行,输出缓冲器从代码转换器接收打包的音频数据,并将打包的音频数据写入WLAN接口。

    BVDII Enhancement with a Cascode DMOS
    64.
    发明申请
    BVDII Enhancement with a Cascode DMOS 审中-公开
    BVDII增强与Cascode DMOS

    公开(公告)号:US20090159968A1

    公开(公告)日:2009-06-25

    申请号:US11960432

    申请日:2007-12-19

    Abstract: Double diffused MOS (DMOS) transistors feature extended drain regions to provide depletion regions which drop high drain voltages to lower voltages at the gate edges. DMOS transistors exhibit lower drain breakdown potential in the on-state than in the off-state than in the off-state due to snapback by a parasitic bipolar transistor that exists in parallel with the DMOS transistor. The instant invention is a cascoded DMOS transistor in an integrated circuit incorporating an NMOS transistor on the DMOS source node to reverse bias the parasitic emitter-base junction during on-state operation, eliminating snapback. The NMOS transistor may be integrated with the DMOS transistor by connections in the interconnect system of the integrated circuit, or the NMOS transistor and DMOS transistor may be fabricated in a common p-type well and integrated in the IC substrate. Methods of fabricating an integrated circuit with the incentive cascoded DMOS transistor are also disclosed.

    Abstract translation: 双扩散MOS(DMOS)晶体管具有扩展的漏极区域,以提供耗尽区域,其将高漏极电压降低到栅极边缘处的较低电压。 由于与DMOS晶体管并联存在的寄生双极晶体管的回跳,DMOS晶体管在导通状态下的漏极击穿电位低于截止状态下的漏极击穿电位。 本发明是在DMOS源节点上结合有NMOS晶体管的集成电路中的级联DMOS晶体管,以在接通状态操作期间反向偏置寄生发射极 - 基极结,从而消除了快速恢复。 NMOS晶体管可以通过集成电路的互连系统中的连接与DMOS晶体管集成,或者NMOS晶体管和DMOS晶体管可以制造在共同的p型阱中并集成在IC衬底中。 还公开了使用激励级联DMOS晶体管制造集成电路的方法。

    PACKETIZED AUDIO DATA OPERATIONS IN A WIRELESS LOCAL AREA NETWORK DEVICE
    66.
    发明申请
    PACKETIZED AUDIO DATA OPERATIONS IN A WIRELESS LOCAL AREA NETWORK DEVICE 有权
    无线本地区域网络设备中的封装音频数据操作

    公开(公告)号:US20080273508A1

    公开(公告)日:2008-11-06

    申请号:US12174629

    申请日:2008-07-16

    CPC classification number: H04W88/06 H04W28/14 H04W84/12

    Abstract: A wireless local area network (WLAN) transceiving integrated circuit includes a WLAN interface, an input buffer, an input buffer controller, and a processor. The WLAN transceiving integrated circuit may also include an output buffer, an output buffer controller, a transcoder, and/or an audio Coder-Decoder (CODEC). The WLAN transceiving integrated circuit is installed in a WLAN device that services voice communications. The input buffer receives packetized audio data from the WLAN interface. When the input buffer satisfies a buffer vacancy threshold, the processor and the input buffer controller cooperatively operate to fill at least a portion of the input buffer with packetized audio data. The processor copies packetized audio data from the input buffer and fills the input buffer with the copied packetized audio data to maintain an audio pattern in the input buffer. The input buffer controller fills the input buffer when the processor is available and after copying/filling is no longer effective. The processor operates to maintain the audio pattern when additional packetized audio data is received by the WLAN interface. These operations are also performed for the output buffer, which receives packetized audio data from the transcoder and writes the packetized audio data to the WLAN interface.

    Abstract translation: 无线局域网(WLAN)收发集成电路包括WLAN接口,输入缓冲器,输入缓冲器控制器和处理器。 WLAN收发集成电路还可以包括输出缓冲器,输出缓冲器控制器,代码转换器和/或音频编解码器(CODEC)。 WLAN收发集成电路安装在服务语音通信的WLAN设备中。 输入缓冲区从WLAN接口接收分组化音频数据。 当输入缓冲器满足缓冲空缺阈值时,处理器和输入缓冲器控制器协同工作,以便用分组化音频数据填充输入缓冲器的至少一部分。 处理器从输入缓冲器复制分组化的音频数据,并用复制的分组化音频数据填充输入缓冲器,以保持输入缓冲器中的音频模式。 当处理器可用并且复制/填充不再有效之后,输入缓冲器控制器填充输入缓冲器。 当附加的分组化音频数据被WLAN接口接收时,处理器操作以维持音频模式。 这些操作也对输出缓冲器执行,输出缓冲器从代码转换器接收打包的音频数据,并将打包的音频数据写入WLAN接口。

    Integrated circuit having a top side wafer contact and a method of manufacture therefor
    67.
    发明授权
    Integrated circuit having a top side wafer contact and a method of manufacture therefor 有权
    具有顶侧晶片接触的集成电路及其制造方法

    公开(公告)号:US07345343B2

    公开(公告)日:2008-03-18

    申请号:US11195283

    申请日:2005-08-02

    CPC classification number: H01L27/1203 H01L21/743 H01L21/76838

    Abstract: The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the semiconductor substrate (130, 1030) having one or more transistor devices (140, 1040) located therein or thereon. The integrated circuit (100, 1000) may further include an interconnect (170, 1053) extending entirely through the semiconductor substrate (130, 1030) and the dielectric layer (120, 1020), thereby electrically contacting the wafer substrate (110, 1010).

    Abstract translation: 因此,本发明提供一种集成电路及其制造方法。 在一个实施例中,集成电路(100,1000)没有限制地包括位于晶片衬底(110,1010)之上的电介质层(120,1020),以及位于介电层上的半导体衬底(130,1030) 120,120),具有位于其中或其上的一个或多个晶体管器件(140,1040)的半导体衬底(130,1030)。 集成电路(100,1000)还可以包括完全延伸穿过半导体衬底(130,1030)和介电层(120,1020)的互连(170,1053),从而与晶片衬底(110,1010)电接触, 。

    REMOTE MOBILE MEDICAL COMMUNICATION APPARATUS, SYSTEM AND METHOD
    68.
    发明申请
    REMOTE MOBILE MEDICAL COMMUNICATION APPARATUS, SYSTEM AND METHOD 审中-公开
    远程移动医疗通信设备,系统和方法

    公开(公告)号:US20080018454A1

    公开(公告)日:2008-01-24

    申请号:US11309208

    申请日:2006-07-13

    CPC classification number: G06F19/3418 A61B5/0022 A61B5/747

    Abstract: A remote mobile medical communication apparatus is suitable for use in communicating with a remote terminal for monitoring and treating a patient. The apparatus comprises a communicating unit, for transmitting a local communication information to the remote terminal, and receiving a remote communication information from the remote terminal. A patient-monitor interface unit receives at least one patient vital-sign signal from the patient, and then transmits to the remote terminal via the communicating unit. A bi-directional audio/video communication unit is for communicating with the remote terminal with an audio/video information via the communicating unit. An instruction from the remote terminal is instructed if the patient needs a treatment. A system and method use the function of the remote mobile medical communication apparatus.

    Abstract translation: 远程移动医疗通信装置适用于与用于监视和治疗患者的远程终端进行通信。 该装置包括通信单元,用于向远程终端发送本地通信信息,以及从远程终端接收远程通信信息。 患者监视器接口单元从患者接收至少一个患者生命体征信号,然后经由通信单元发送到远程终端。 双向音频/视频通信单元用于经由通信单元与远程终端通信具有音频/视频信息。 如果患者需要治疗,则指示远程终端的指令。 系统和方法使用远程移动医疗通信设备的功能。

    Baseband Controller in a Wireless Local Area Network
    69.
    发明申请
    Baseband Controller in a Wireless Local Area Network 失效
    无线局域网中的基带控制器

    公开(公告)号:US20070087692A1

    公开(公告)日:2007-04-19

    申请号:US11539783

    申请日:2006-10-09

    Applicant: John Lin

    Inventor: John Lin

    CPC classification number: H04J3/0685 H04W28/06 H04W28/14 H04W84/12 H04W84/18

    Abstract: A baseband controller includes a microsequencer with special hardware resources circuitry and a configuration that supports real-time Bluetooth functionality for an upper limit of Bluetooth slave devices. The microsequencer includes a 72-bit correlator that may also be used as an accumulator, wherein the topology provides that the correlator can communicate with a 72-bit arithmetic logic unit that correspondingly enables the correlator to act as an accumulator. The microsequencer also includes a plurality of clocks and timers for facilitating Bluetooth timing functionality, and at least four registers for temporarily storing computational data, where each of the storage registers have different sizes for accommodating different-sized packets of computational data.

    Abstract translation: 基带控制器包括具有特殊硬件资源电路的微定序器和支持蓝牙从设备上限的实时蓝牙功能的配置。 微定序器包括也可以用作累加器的72位相关器,其中拓扑结构提供相关器可以与72位算术逻辑单元进行通信,这相应地使得相关器能够充当累加器。 微定序器还包括用于促进蓝牙定时功能的多个时钟和定时器,以及用于临时存储计算数据的至少四个寄存器,其中每个存储寄存器具有不同的大小以适应计算数据的不同大小的分组。

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