公开(公告)号：US20110073955A1

公开(公告)日：2011-03-31

申请号：US12962159

申请日：2010-12-07

申请人： Sameer P. Pendharkar ,  John Lin ,  Philip L. Hower ,  Steven L. Merchant

发明人： Sameer P. Pendharkar ,  John Lin ,  Philip L. Hower ,  Steven L. Merchant

IPC分类号： H01L27/06

CPC分类号： H01L21/8249 ,  H01L21/76232 ,  H01L27/0623

摘要： A semiconductor device comprising a first transistor device (130) on or in a semiconductor substrate (115) and a second transistor device (132) on or in the substrate. The device further comprises an insulating trench (200) located between the first transistor device and the second transistor device. At least one upper corner (610) of the insulating trench is a rounded corner in a lateral plane (620) of the substrate.

摘要翻译： 一种半导体器件，包括在半导体衬底（115）上或半导体衬底（115）中的第一晶体管器件（130）和衬底上或衬底中的第二晶体管器件（132）。 该器件还包括位于第一晶体管器件和第二晶体管器件之间的绝缘沟槽（200）。 绝缘沟槽的至少一个上角（610）是衬底的横向平面（620）中的圆角。

公开(公告)号：US06797547B2

公开(公告)日：2004-09-28

申请号：US10679220

申请日：2003-10-03

申请人： Sheldon D. Haynie ,  Steven L. Merchant ,  Sameer P. Pendharkar ,  Vladimir Bolkhovsky

发明人： Sheldon D. Haynie ,  Steven L. Merchant ,  Sameer P. Pendharkar ,  Vladimir Bolkhovsky

IPC分类号： H01L2100

CPC分类号： H01L29/66681 ,  H01L29/0657 ,  H01L29/4175 ,  H01L29/66674 ,  H01L29/66772 ,  H01L29/7824 ,  H01L29/78624 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post. The process can be used with conventional bulk silicon wafers and processes, and the blade devices can be integrated with conventional planar devices formed on other areas of the wafer.

公开(公告)号：US6150200A

公开(公告)日：2000-11-21

申请号：US55119

申请日：1998-04-03

申请人： Steven L. Merchant

发明人： Steven L. Merchant

IPC分类号： H01L29/08 ,  H01L21/332 ,  H01L21/8222

CPC分类号： H01L29/7816 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/66681 ,  H01L29/0634 ,  H01L29/0696

摘要： A semiconductor device (10) is formed in a semiconductor substrate (11) and an epitaxial layer (14). The semiconductor device includes a p-type body region (16), a source region (17), a channel region (19), and a drain region (34) formed in the epitaxial layer (14). A doped region (13) is formed in the semiconductor substrate (11) to reduce the drift resistance of the semiconductor device (10). The drain region (34) is formed from a plurality of doped regions (30-33) that can be formed with high energy implants.

摘要翻译： 半导体器件（10）形成在半导体衬底（11）和外延层（14）中。 半导体器件包括形成在外延层（14）中的p型体区（16），源区（17），沟道区（19）和漏区（34）。 在半导体衬底（11）中形成掺杂区（13）以降低半导体器件（10）的漂移电阻。 漏极区域（34）由可以用高能量植入物形成的多个掺杂区域（30-33）形成。

公开(公告)号：US6140184A

公开(公告)日：2000-10-31

申请号：US88027

申请日：1998-06-01

申请人： Phillipe Dupuy ,  Steven L. Merchant ,  Robert W. Baird

发明人： Phillipe Dupuy ,  Steven L. Merchant ,  Robert W. Baird

IPC分类号： H01L27/02 ,  H01L21/8234 ,  H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L27/0211

摘要： A field effect transistor (30) has an array of transistors (31) made up of bonding pads (45-47) and sub-arrays of transistors (41-43). The bonding pads (45-47) are distributed between the sub-arrays of transistors (41-43) to reduce the maximum temperature that any portion of the FET (30) is exposed to while the FET (30) is in a conducting state. A similar effect can be appreciated by adjusting the threshold voltage or pinch-off resistance of the transistors in a portion (101) of an array of transistors (95).

摘要翻译： 场效应晶体管（30）具有由键合焊盘（45-47）和晶体管（41-43）的子阵列构成的晶体管阵列（31）。 接合焊盘（45-47）分布在晶体管（41-43）的子阵列之间，以降低FET（30）处于导通状态时FET（30）的任何部分暴露的最大温度 。 可以通过调整晶体管阵列（95）的一部分（101）中的晶体管的阈值电压或夹断电阻来获得类似的效果。

公开(公告)号：US5767547A

公开(公告)日：1998-06-16

申请号：US448268

申请日：1995-05-23

申请人： Steven L. Merchant ,  Emil Arnold

发明人： Steven L. Merchant ,  Emil Arnold

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861 ,  H01L27/01 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/66772 ,  H01L29/7394 ,  H01L29/78612 ,  H01L29/78624 ,  H01L29/861 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/42368

摘要： The present invention is directed to a thin film transistor having a linear doping profile between the gate and drain regions. This is constructed in a particular manner in order to achieve a thin film transistor having a significantly high breakdown voltage of the order of 700 to 900 volts, much greater than that achieved in the prior art.

摘要翻译： 本发明涉及一种在栅极和漏极区域之间具有线性掺杂分布的薄膜晶体管。 这是以特定方式构造的，以便实现具有大约700至900伏特的显着高的击穿电压的薄膜晶体管，比现有技术中实现的要大得多。

公开(公告)号：US5213986A

公开(公告)日：1993-05-25

申请号：US867729

申请日：1992-04-10

申请人： Ronald D. Pinker ,  Steven L. Merchant ,  Arnold, Emil

发明人： Ronald D. Pinker ,  Steven L. Merchant ,  Arnold, Emil

IPC分类号： H01L21/22 ,  H01L21/762

CPC分类号： H01L21/76256 ,  H01L21/2205 ,  H01L21/76251 ,  Y10S148/012

摘要： A very thin silicon film SOI device can be made utilizing a bond and etch-back process. In the presently claimed invention, boron dopant is introduced into a surface of a silicon device wafer and the doped surface is bonded onto another silicon wafer at an oxide surface. The device wafer is thinned by etching down to the doped region and, by subsequent annealing in hydrogen, boron is diffused out of the silicon surface layer to produce very thin SOI films.

摘要翻译： 可以利用粘结和回蚀工艺制造非常薄的硅膜SOI器件。 在目前要求保护的发明中，硼掺杂剂被引入到硅器件晶片的表面中，并且掺杂表面在氧化物表面上结合到另一个硅晶片上。 通过蚀刻到掺杂区域使器件晶片变薄，并且通过随后在氢中退火，硼从硅表面层扩散出来以产生非常薄的SOI膜。

公开(公告)号：US06603157B2

公开(公告)日：2003-08-05

申请号：US10004517

申请日：2001-11-02

申请人： Phillipe Dupuy ,  Steven L. Merchant ,  Robert W. Baird

发明人： Phillipe Dupuy ,  Steven L. Merchant ,  Robert W. Baird

IPC分类号： H01L2710

CPC分类号： H01L27/0211

摘要： A field effect transistor (30) has an array of transistors (31) made up of bonding pads (45-47) and sub-arrays of transistors (41-43). The bonding pads (45-47) are distributed between the sub-arrays of transistors (41-43) to reduce the maximum temperature that any portion of the FET (30) is exposed to while the FET (30) is in a conducting state. A similar effect can be appreciated by adjusting the threshold voltage or pinch-off resistance of the transistors in a portion (101) of an array of transistors (95).

摘要翻译： 场效应晶体管（30）具有由键合焊盘（45-47）和晶体管（41-43）的子阵列构成的晶体管阵列（31）。 接合焊盘（45-47）分布在晶体管（41-43）的子阵列之间，以降低FET（30）处于导通状态时FET（30）的任何部分暴露的最大温度 。 可以通过调整晶体管阵列（95）的一部分（101）中的晶体管的阈值电压或夹断电阻来获得类似的效果。

公开(公告)号：US5710451A

公开(公告)日：1998-01-20

申请号：US629819

申请日：1996-04-10

申请人： Steven L. Merchant

发明人： Steven L. Merchant

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/786 ,  H01L29/74 ,  H01L31/111 ,  H01L27/01 ,  H01L27/12

CPC分类号： H01L29/0847 ,  H01L29/786 ,  H01L29/78624 ,  H01L29/78645 ,  H01L29/402

摘要： A Semiconductor-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate, and a lateral MOSFET on the buried insulating layer. The MOSFET includes a semiconductor surface layer on the buried insulating layer and has a source region of a first conductivity type, a channel region of a second conductivity type opposite to that of the first, an insulated gate electrode over the channel region and insulated therefrom, a lateral drift region of the second conductivity type, and a drain region of the first conductivity type laterally spaced apart from the channel region by the drift region. A semiconductor linkup region of the first conductivity type is provided between the channel region and the drift region and extends substantially through the semiconductor surface layer, and the source region of the device is electrically coupled to the drift region. This device configuration is particularly useful in providing a high-voltage p-channel MOS transistor using thin SOI high-voltage technology normally associated with fabricating n-channel devices.

摘要翻译： 绝缘体半导体器件（SOI）器件包括半导体衬底，衬底上的掩埋绝缘层和掩埋绝缘层上的横向MOSFET。 MOSFET包括在掩埋绝缘层上的半导体表面层，并且具有第一导电类型的源极区域，与沟道区域相反的第二导电类型的沟道区域，绝缘栅极电极并与其绝缘的半导体表面层， 所述第二导电类型的横向漂移区域和所述第一导电类型的漏极区域由所述漂移区域与所述沟道区域横向间隔开。 第一导电类型的半导体连接区域设置在沟道区域和漂移区域之间，并且基本上延伸穿过半导体表面层，并且器件的源极区域电耦合到漂移区域。 该器件配置在通常与制造n沟道器件相关联的薄SOI高压技术中提供高压p沟道MOS晶体管特别有用。

公开(公告)号：US5300448A

公开(公告)日：1994-04-05

申请号：US15061

申请日：1993-02-08

申请人： Steven L. Merchant ,  Emil Arnold

发明人： Steven L. Merchant ,  Emil Arnold

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861 ,  H01C21/266

CPC分类号： H01L29/66772 ,  H01L29/7394 ,  H01L29/78612 ,  H01L29/78624 ,  H01L29/861 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/42368

摘要： The present invention is directed to a method and thin film transistor having a linear doping profile between the gate and drain regions. This is constructed in a particular manner in order to achieve a thin film transistor having a significantly high breakdown voltage of the order of 700 to 900 volts, much greater than that achieved in the prior art.

摘要翻译： 本发明涉及一种在栅极和漏极区域之间具有线性掺杂分布的方法和薄膜晶体管。 这是以特定方式构造的，以便实现具有大约700至900伏特的显着高的击穿电压的薄膜晶体管，比现有技术中实现的要大得多。

公开(公告)号：US07910417B2

公开(公告)日：2011-03-22

申请号：US12176488

申请日：2008-07-21

申请人： Philip L. Hower ,  David A. Walch ,  John Lin ,  Steven L. Merchant

发明人： Philip L. Hower ,  David A. Walch ,  John Lin ,  Steven L. Merchant

IPC分类号： H01L21/337

CPC分类号： H01L29/808 ,  H01L29/1066

摘要： A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET.

摘要翻译： 结型场效应晶体管（JFET）可以制造具有阱区，阱区包括平均掺杂剂浓度基本上小于阱区的剩余部分的平均掺杂浓度的沟道区。 与阱区域的其余部分相比，沟道区域的较低平均掺杂浓度降低了JFET的夹断电压。